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080602: IITC shows the way to 3D
Ed’s Threads 080602 Musings by Ed Korczynski on June 2, 2008
IITC shows the way to 3D
The 11th International Interconnect Technology Conference (IITC) started today in Burlingame near the San Francisco airport. Once again, the leading-edge of on-chip interconnect technology developments were presented, with details on new materials, processes, and structures. 3D interconnects and through-silicon vias (TSV) were discussed in serious detail, while work continues on air-gap dielectrics and carbon nanotubes (CNT) along with new copper barrier materials. 3D with TSV may be considered as the ultimate interconnect concept, since stacked chips provide optimal functionality/volume, and provide for relatively low-cost heterogeneous integration of diverse technologies such as sensors. TSV and the many variations thereof have been hot topics in 3D for many years, with “via-last” being done today in production for memory stacks needing typically <100 TSV per chip. In contrast, “via-first” TSV processing flows may produce thousands per chip, and there are many integration schemes possible. IITC publicity chairman (and IBM researcher) Michael Shapiro commented that, “3D is such a ‘silicon-centric’ process technology that the IITC is really the place to have the discussion, because all the experts of silicon etching and planarization are here and have always been here.” Fraunhofer IZM (Institute for Reliability and Microintegration) in Munich has been leading the world in 3D-IC work for over ten years, and researchers from there have been developing detailed system-level heterogeneous integration schemes for wireless applications (for the European 3D integrated sensor program “e-CUBES”). Their target is die-to-wafer (D2W) stacking of a tire pressure monitoring system (TPMS). The wafer has the microcontroller chips, onto which are stacked chips for the RF transceiver, pressure sensor, and bulk acoustic resonator (BAR). For TSV, they integrate chips with both solid metal trenches (typically W filled ~20 µm deep) or hollow vias coated with doped poly-silicon (through the 300 µm thick pressure sensor).
Researchers from Georgia Tech built upon work they first showed three years ago at IITC, and together with IBM and Nanonexus showed real results of using integrated microchannel cooling to remove heat from 3D-IC stacks. Fluidic microchannels were fabricated at the wafer-level using four lithography steps, and the resulting chips showed thermal resistance of just 0.24°C/W compared to 0.6°C/W for equivalent 65nm node air-cooled chips. With reduced thermal resistance, significant advances in speed, power, and/or operating temperature can be achieved; for example, power could be reduced ~20% at the same frequency, or the frequency could increase 10% at the same power.
Basic materials integration challenges of 3D integration were shown in two presentations by IMEC. Micro-Raman spectroscopy (µRS) was used to determine the plastic yield criterion for an accurate finite element modeling (FEM) of the stress near Cu-filled TSV. Due to the inherent mismatch between CTE of Cu (16.7 ppm/°C) and Si (2.3 ppm/°C), some strain will be inherent, and it may degrade electrical carrier mobility. Defining an “exclusion zone” of transistors from the TSV such that mobility degrades <5%,>
IMEC researchers also looked at reliability in a presentation on “Resistance to electromigration of purely intermetallic micro-bump interconnections for 3D-device stacking.” Both Cu-Sn and Co-Sn were shown to withstand 1000 hours of testing at the extremely aggressive conditions of 150°C and 0.63mA/µm2).
Scott Pozder of Freescale Semiconductor showed an excellent poster on Cu-Sn microconnects formed simultaneously with an adhesive dielectric bond using thermal compression bonding of flipped dice on a wafer. After D2W bonding using Cookson F602 material at micropad pitches of 59, 64, and 69µm, the robustness of the bond was shown by grinding the bonded dice to 50µm thin using a Disco Hi-Tec tool. While no TSV are used in this die-to-wafer stack, this pragmatic approach based on standard unit-processes which can be found in the open foundry market shows one clear way forward toward 3D today.
Tohoku University researchers showed one way to cut costs in D2W bonding: use a rough lithographic step to form hydrophobic and hydrophilic areas on the wafer, add an aqueous coating and then roughly place the dice. The surface tension of the liquid induces the dice to self-align, and control of the ambient can allow for the liquid to evaporate which temporarily bonds the dice to the wafer. The average alignment accuracy on 100 dice was ~0.5µm, with most dice aligned within <1µm and all <1.5µm.
D2W stacking of 3D chips allows for the used of known good dice (KGD) and the associated minimization of yield losses anticipated with wafer-to-wafer (W2W) stacking. D2W stacking technology will first follow Freescale’s lead by flipping the top die for two levels of silicon, but TSV and three or more levels will certain follow.
Much of the limitation in the use of TSV today remains with the designers; lacking EDA tools, it is not only difficult to optimize a design for 3D, it is challenging to just try to quantify the potential benefits in advance. Until EDA tools are ready the greatest potential value of 3D stacking will not be seen, and most commercial TSV will continue to be used for memory stacks and CMOS image sensors.
This is the last year in which interconnect technologists living in the San Francisco bay area have the exclusive luxury of the International Interconnect Technology Conference being local. Next year (June 1-3, 2009), the 12th IITC will occur in Sapporo, Japan at the Royton Sapporo hotel. The 2010 meeting will be back in the San Francisco bay area, and then the 2011 meeting is expected to occur somewhere in Europe.
—E.K. Labels: 3D, IITC, interconnect, silicon, stack, through-silicon via, TSV
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080602: IITC shows the way to 3D
080407: CNT and graphene dreams may be real
Ed’s Threads 080407 Musings by Ed Korczynski on April 7, 2008CNT and graphene dreams may be realCarbon nano-tubes (CNT) are the only viable (pun-intended) new materials being developed to replace copper as the electrical interconnects for future ICs. There are no known room-temperature superconductors, and optical interconnects require relatively slow and expensive lasers and detectors, and CNTs are the future. The theory and practice of growing CNTs was thoroughly reviewed at this spring’s Materials Research Society (MRS) meeting, and the applications as electronic IC interconnects will be seen at the International Interconnect Technology Conference (IITC) to be held in Burlingame, California in June. The deadline for submitting late news to IITC is this Friday. Carbon can form an amazing variety of stable crystals and molecules based on different bond energies and angles between atoms. In crystalline form, sp2 electron orbitals can form 2D planes of graphite or sp3 electron orbitals can form 3D tetrahedral of diamond. The 2D form of solid carbon shows very interesting properties when reduced down to less than a few atomic layers. Graphene is one or two atomic layers only, which results in geometrically induced electron energy-band modification and the ability to form semiconducting devices. Graphene is a great potential “long-shot” technology first reported in January 2006 Solid State Technology…sure to generate many Ph.D. theses and likely to benefit DARPA programs…but still quite a way away from proven as commercially manufacturable. As Gordon Moore reminds us in this recent interview, “The actual idea of an MOS transistor was patented in the mid-'20s,” though it was not until over 40 years later that Intel started making a business out of it. Take 60 carbon atoms and you can coax them together into a cage-like spheroid called a “buckyball” or fullerene (C60)—initially predicted by R. Buckminster Fuller based on the potential for stable bond-angles in regular polyhedra—which has the same 2D form as graphene. Larger and more complex carbon cage molecules can be formed, and seem to be formed naturally by stars in space. Take a continuous supply of carbon atoms and you can coax them together using a catalyst particle into growing as a nano-tube with that same basic 2D form. You can grow both single-walled CNT (SWCNT) and multi-walled CNT (MWCNT). Both grow off of metal catalyst particles, which must somehow first be deposited in the bottom of vias to form interconnects between lines; making the connection on the top side seems like it will be inherently a bit tricky. At IITC this year, researchers from MIRAI-Selete and Waseda University (Japan) will show actual integration results for CNT in 160nm diameter vias at temperatures as low as 365°C. The team will report that the CNT fabrication process didn’t degrade a fragile low- k (2.6) dielectric and that the vias sustained a current density as high as 5.0 MA/cm2 at 105°C for 100 hours with no deterioration. SEM cross-sections of 160nm-diameter CNT vias fabricated with growth temperatures of (a) 450°C and (b) 400°C (IITC2008 Paper #12.4, “Robustness of CNT Via Interconnect Fabricated by Low Temperature Process over a High-Density Current,” A. Kawabata et al.)
One of the reasons that MRS meetings are exciting for materials scientists and engineers is that truly leading results are shown. Oleg Kuznetsov et al.—from Honda Research Institute in Columbus OH (USA) and Goteborg University (Sweden) and Duke University (USA)—presented information on the size-dependence peculiarities of small catalyst clusters and their effect on SWCNT growth. Though exact mechanisms are not fully understood yet, we know that nano-scale catalysts particles play key roles in growth, and that sizes alter growth properties. The general background assumption is a vapor-liquid-solid (VLS) model for growth: carbon in the vapor phase is absorbed into the catalyst particle as a liquid from which solid SWCNT grows out. An observed ‘paradox’ is that with decrease of catalyst size from 3nm to 1nm the required minimum temperature for SWCNT growth increases. Molecular dynamics simulations revealed that reducing the catalyst particle size reduces its solubility of carbon atoms and thereby requires higher temperature for SWCNT growth.
Since the researchers used Fe as the catalyst for SWCNT growth, their rigorous modeling work included a re-working of the classic Fe-C phase diagram where they showed that SWCNTs grow in a liquidous region above the Eutectic point. The Fe-C phase diagram is arguably the foundation of modern materials engineering, since it shows how to make the varieties of steel which are the physical backbone of construction in our age, and is taught in all undergraduate materials science courses. While I haven’t been looking very hard, but this is the first time I’ve seen something new in a Fe-C phase diagram since I left MIT in 1984.
—E.K.
Labels: CNT, graphene, IITC, interconnect, MRS, through-silicon via
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080407: CNT and graphene dreams may be real
080222: TSV forecast for millions of wafers
Ed’s Threads 080222 Musings by Ed Korczynski on February 22, 2008TSV forecast for millions of wafers
Through-silicon vias (TSV) can be used to connect 3D multi-chip module stacks with improved performance and reduced timing delays. A new report by analysts at TechSearch International, Through Silicon Via Technology: The Ultimate Market for 3D Interconnect, provides a forecast for millions of silicon wafers to be made with TSV in the year 2014. For the next few years, however, it is likely that image-sensors and memory chip stacks will be the major high-volume applications, building on the estimated less than 50,000 wafers to be fabbed with TSV this year according to TechSearch President Jan Vardaman. The industry is now moving past the feasibility (R&D) phase for TSV technology and into the commercialization phase, where economic realities will determine which technologies are adopted. Low-cost fine via hole formation and highly reliable via filling technologies have been demonstrated; process equipment and materials are available. Global research organizations are looking at applications for TSVs including image sensors, flash, DRAM, microprocessors, FPGAs, and power amplifiers. There is no question that 3D TSV will be adopted, but the timing for mass production depends on how the cost of the new technology compares with that of existing technologies. In particular, as confirmed by Vardaman, if there are only 2 silicon layers to be assembled it is generally more cost-effective today to use flip-chip with wire-bonders. Another 1 or 2 chip layers can be easily added to the bottom side of an interposer, still without the need for TSV. In so doing, the wire-bonds are not in any way limits on system performance, since flip-chip bumps and re-distribution layers (RDL) are still used to route signals from chip to chip within the package. Intel has announced that its newest 45nm microprocessor chip is the first to use a thick copper RDL layer along with a polymer interconnect dielectric (presumably spun-on). A thinned memory cache chip with metal bumps (presumably C4NP or equivalent) can then be flipped onto the microprocessor and lead-free connections re-flowed to the RDL for low-latency electrical interconnects. Wire bonds then connect the stack to the package pins through an interposer. An interposer today is commonly built-up using thin-film laminates, but there is renewed interest in the use of silicon as interposers…which would require TSV. Many companies, including MEMS foundries and equipment suppliers, today offer foundry services to create silicon interposers containing TSVs. Silicon is a wonderful material to use as an interposer between silicon chips: same coefficient of thermal expansion eliminates shear stresses on bumps due to heating, excellent relative thermal conductivity to help heat leave the chips, and excellent mechanical strength. The only problem has been the cost compared to build-up laminates. If costs can be reduced, then demand should be very elastic for silicon interposers with TSV, and we could see interposers instead of product wafers as the main near-term market for silicon TSV outside of memory stacks. Image sensors for camera modules are already in volume production, with major investments by Tessera and Micron in wafer-level-packaging TSV manufacturing technology. The next volume application seems to be memory stacks, but it is only high-cost niche IC applications today that can justify the added cost of TSVs over wire-bonds. Design, thermal, and test issues remain a barrier to TSV adoption in some applications, though progress is being made. Flip-chip was first introduced by IBM in the late 1960s, and it took approximately 40 years for the technology to become dominant such that more silicon wafers end up flipped instead of wirebonded today. TSV technology is already in use, but it will probably be decades before the majority of chips use it as a solution to the cost/performance trade-off challenge. The official semiconductor silicon wafer demand forecast is for ~10 billion sq.in. of silicon by the year 2010, which corresponds to ~200 million silicon wafers (in 200mm wafer equivalents) to be fabbed. It is unlikely that more than a few million of them will need internal TSV, but if costs can be reduced it is possible that many more could use silicon interposers with TSV. —E.K. Labels: blind TSV, interconnect, interposer, silicon, through-silicon via
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080222: TSV forecast for millions of wafers
070928: Who needs through-silicon vias?
Ed’s Threads 070928 Musings by Ed Korczynski on September 28, 2007Who needs through-silicon vias?Besides MEMS and opto-electronics, who really needs through-silicon vias (TSV) for commercial ICs? This was the burning question around which presenters danced for an afternoon at the International Wafer-Level Packaging Conference (IWLPC) held this September in San Jose, California. Starting with IC and wafer-level packaging technologies already in use, experts seem confident that technology integration can create a manufacturable TSV fab flow. However, while 3D-WLP is already commercially viable (pun intended), TSV do not seem to be needed for the near future; wire-bonding already can handle up to 16 chips, and 2 level connections can be easily flip-chipped for high-performance (like for a microprocessor cache). Ken Gilleo of ET-Trends LLC discussed the “coming paradigm shift in packaging” caused by TSV and wafer-level packaging, asserting that significant technology development has occurred with unit processes in recent years such that the main technology hurdles remain with integration. Leslie Lea, CTO and deputy CEO for STS, explained how deep reactive-ion etch (DRIE) for TSV on 300mm wafers will still use a derivative of the sequential “Bosch Etch” process, using the C4F8 plasma for polymer sidewall deposition, then SF6 plasma for etching. This process can produce vias to 80:1 aspect ratios, but sidewall scallops inevitably exist. Cu-TSV plating time shown was 4 hr for 50µm via, while 10µm via filled in 1 hr using NEXX systems and Enthone chemistry to create via fills without voids—with vias of 10-50µm depths all nicely filled on the same chip. TSVs have been demonstrated in four different approaches and integration schemes: blind, poly, tungsten, and copper. Jim Walker, research vice president for Gartner Dataquest, suggests that we all should use the standard PCB term “blind vias” for essentially the same structures in silicon. Unlike the other three, ‘blind’ vias don’t include the conductor, but etch/drill out openings through an upper silicon chip, typically to allow a wire bonder to make connections to bond-pads on a lower silicon chip. These are not new. Back in 1989 I developed a pilot process for a 3-level WLP using blind TSVs for an accelerometer chip for SenSym ( Analog Devices’ designers were much smarter and their planar chip design was far more manufacturable and lower cost, so sadly for me at the time the chip was killed at pilot). Blind TSVs can be combined with flip-chip stacks and C4/C4NP bumping to get to three or more silicon layers with relatively low cost and minimal disruption of current packaging flows. Blind TSVs are another way that wire bonders may continue to function as the ‘work-horses’ of packaging lines, working with KOH or EDPW wet-etches to form sloped openings along the crystalline planes in silicon. In an exclusive meeting with WaferNEWS, Giles Humpston, director of R&D for Tessera, explained that the company’s ~$100M investment in optical-WLP technology built on the acquired ShellCase technology for blind TSV applied to the unique requirements of image-sensors and quartz substrates. Filled vias with poly, tungsten, or copper are the TSV ideal that many of us have conceived of for 3D ICs. If design and test software could handle it, and if integration can be as low as $200/wafer ( EMC-3D goal), then these TSV might be first used to stack like devices like memory parts. Phil Marcoux, longtime packaging technology expert currently with Chip Scale/TPL Group, thinks that full integration won’t be ready for five years. Gilleo countered that in 2008, “some memory will use TSV.” Citing first principles of electrical interconnection—going back to the use of copper in the first US printed circuit board patent in 1902—Gilleo is convinced that ultimately copper is the way to go for filled TSV. Used both for PCBs and on-chip interconnects, there is a tremendous amount of proven technology that can be borrowed to speed up TSV integration. “It’s well controlled in electroplating, and it has the right balance of chemical and mechanical properties,” informed Gilleo. It becomes the nature selection for the conductor. “It has almost everything you want for building conductor pathways.” All of this was known to the early pioneers of the planar IC at Fairchild Semiconductor. And yet they chose aluminum over copper, because copper is more reactive and can more easily diffuse into silicon and damage transistors. Copper will always have a much higher expansion with temperature compared to silicon, and so high-temperature processes will inherently stress barrier layers. Polysilicon can be annealed and then have the same expansion with temperature as the silicon wafer. Of course, polysilicon conductivity is always lower than copper, so there are trade-offs in the TSV conductor choices. While debating whether to consider integrating poly or copper or even tungsten plugs, a gold wire bonder has already made the connection. Packaging moves fast. --E.K. Labels: 3D, blind TSV, copper, IC, interconnect, stack, through-silicon via
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070928: Who needs through-silicon vias?
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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.
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