Ed’s Threads 080225
Musings by Ed Korczynski on February 25, 2008

Interconnect technology mature
On-chip interconnects made primarily of copper metal insulated with SiOC low-k dielectric material are the current state-of-the-art for the commercial IC manufacturing industry. A report from the TECHCET Group quantifies the materials that are forecasted to be needed to form interconnects for 65nm to 32nm node ICs. Except for some new barrier layers, the only major change on the interconnect horizon is the use of pores or air-gaps in the dielectric material to get to ultra low-k (ULK, a.k.a. extreme low-k or ELK).

Though carbon nano-tubes (CNT) have been considered as new conductors, and self-assembled dielectrics have also been investigated, commercial IC fabs are necessarily slow to change proven technologies, and so it is almost certain that these newer approaches will not be used for commercial IC manufacturing anytime soon.

From first principles and reasonable modeling, we know that Cu is not the ultimate electrical conductor, but lacking room-temperature superconductors and ways to form dense arrays of metallic CNTs, the only near-term solution is to use more and more copper layers as a method of dealing with higher resistance copper in smaller lines. With Cu pushed to the limits, it is axiomatic that current density inside minimum pitch lines is huge such that electromigration induced reliability problems are inherent.

Cu lines in advanced dual-damascene interconnects are already complex structures, with barrier layers to prevent Cu diffusion into low-k dielectrics. An ideal Cu barrier inhibits electromigration, though any barrier is more resistive than the Cu itself, so it should be as thin as possible to minimize resistivity without allowing for Cu diffusion. For the 32nm node, Copper Manganese (CuMn) and Ruthenium barriers have been investigated, in part due to the integration advantage of being able to electro-plate Cu directly on either barrier without the need for a PVD Cu “seed” deposition. If CuMn is used, then some of the Mn diffuses to the surface of the Cu during metal anneal, and removing this surface Mn during the CMP step results in lower via resistance due to a direct Cu-to-Cu bond.

For cap layers, silicon nitride has been used at ≥90 nm, but it has a rather high dielectric constant of ~7, so SiCN with a dielectric constant of ~5 has been used at 65nm. For 32nm the most likely capping barrier may be CuSiN—formed by reacting the post-CMP Cu with SiH4 and NH3—or CoWP.

Dielectrics technology has never met the wishes of the ITRS for a different material for each node. With the k-value stuck at ~2.7 for a blanket SiOC film, the only practical solution to lower k has been to substitute “air” (a low-pressure vacuum, really) as part of the dielectric material. The air can be in random zero-dimensional “pore” (or nanopore) structures in the material, which may be formed by sublimating the homogeneously-nucleated 2nd-phase of a deposited blanket film. The air can be in random or ordered one-dimensional “air columns” in the material, as shown by Edelstein et al. at IBM. The air can also be in patterned two- and three-dimensional “air-gaps” formed by many different process flows, as shown by Hoofman et al. at Philips/NXP.

Conformal dielectric CVD processes can also be tuned to automatically form air-gaps between lines—known as “key-holes” or “bread-loaves” due to the characteristic shape of the gap when viewed in cross-section—for metal line spaces of a certain pitch. Standard dielectric CVD processes are tuned to avoid air-gaps in random line spaces so that gaps do not appear spontaneously in some portions of a random IC design. Key-hole air-gaps as desired dielectric structures were first reported by Shieh et al. of Stanford in the pages of SST in 1999, and the major limit with their use has been the need to impose design constraints on metal line pitch.

However, it now appears certain that nearly all 32nm node ICs will be made with restricted design rules just so that lithography will work. Likewise, CMP and Etch uniformity specifications at 32nm seem to mandate severe restrictions on geometry and the extensive use of “dummy fill” beyond all precedent. If a design must already deal with such limitations, then why not integrate in key-hole air-gaps by CVD? Alternatively, like IBM or Matsushita, you can use a non-critical lithography masking step and etching to define the air-gap locations independent of line pitch.

Lest we forget, aluminum metal is still used as the on-chip interconnect for some 65nm node memory chips. Proven process technology is replaced only when IC performance mandates a change, and so evolutions happens far more often than revolutions.

—E.K.

Labels: copper, dummy fill, interconnect, low-k, ULK

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080225: Interconnect technology mature

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Ed’s Threads 080222
Musings by Ed Korczynski on February 22, 2008

TSV forecast for millions of wafers
Through-silicon vias (TSV) can be used to connect 3D multi-chip module stacks with improved performance and reduced timing delays. A new report by analysts at TechSearch International, Through Silicon Via Technology: The Ultimate Market for 3D Interconnect, provides a forecast for millions of silicon wafers to be made with TSV in the year 2014. For the next few years, however, it is likely that image-sensors and memory chip stacks will be the major high-volume applications, building on the estimated less than 50,000 wafers to be fabbed with TSV this year according to TechSearch President Jan Vardaman.

The industry is now moving past the feasibility (R&D) phase for TSV technology and into the commercialization phase, where economic realities will determine which technologies are adopted. Low-cost fine via hole formation and highly reliable via filling technologies have been demonstrated; process equipment and materials are available. Global research organizations are looking at applications for TSVs including image sensors, flash, DRAM, microprocessors, FPGAs, and power amplifiers.

There is no question that 3D TSV will be adopted, but the timing for mass production depends on how the cost of the new technology compares with that of existing technologies. In particular, as confirmed by Vardaman, if there are only 2 silicon layers to be assembled it is generally more cost-effective today to use flip-chip with wire-bonders. Another 1 or 2 chip layers can be easily added to the bottom side of an interposer, still without the need for TSV.

In so doing, the wire-bonds are not in any way limits on system performance, since flip-chip bumps and re-distribution layers (RDL) are still used to route signals from chip to chip within the package. Intel has announced that its newest 45nm microprocessor chip is the first to use a thick copper RDL layer along with a polymer interconnect dielectric (presumably spun-on). A thinned memory cache chip with metal bumps (presumably C4NP or equivalent) can then be flipped onto the microprocessor and lead-free connections re-flowed to the RDL for low-latency electrical interconnects. Wire bonds then connect the stack to the package pins through an interposer.

An interposer today is commonly built-up using thin-film laminates, but there is renewed interest in the use of silicon as interposers…which would require TSV. Many companies, including MEMS foundries and equipment suppliers, today offer foundry services to create silicon interposers containing TSVs. Silicon is a wonderful material to use as an interposer between silicon chips: same coefficient of thermal expansion eliminates shear stresses on bumps due to heating, excellent relative thermal conductivity to help heat leave the chips, and excellent mechanical strength. The only problem has been the cost compared to build-up laminates. If costs can be reduced, then demand should be very elastic for silicon interposers with TSV, and we could see interposers instead of product wafers as the main near-term market for silicon TSV outside of memory stacks.

Image sensors for camera modules are already in volume production, with major investments by Tessera and Micron in wafer-level-packaging TSV manufacturing technology. The next volume application seems to be memory stacks, but it is only high-cost niche IC applications today that can justify the added cost of TSVs over wire-bonds. Design, thermal, and test issues remain a barrier to TSV adoption in some applications, though progress is being made.

Flip-chip was first introduced by IBM in the late 1960s, and it took approximately 40 years for the technology to become dominant such that more silicon wafers end up flipped instead of wirebonded today. TSV technology is already in use, but it will probably be decades before the majority of chips use it as a solution to the cost/performance trade-off challenge. The official semiconductor silicon wafer demand forecast is for ~10 billion sq.in. of silicon by the year 2010, which corresponds to ~200 million silicon wafers (in 200mm wafer equivalents) to be fabbed. It is unlikely that more than a few million of them will need internal TSV, but if costs can be reduced it is possible that many more could use silicon interposers with TSV.

—E.K.

Labels: blind TSV, interconnect, interposer, silicon, through-silicon via

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080222: TSV forecast for millions of wafers

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Ed’s Threads 080211
Musings by Ed Korczynski on February 11, 2008

IITC process units and integration
The International Interconnect Technology Conference (IITC) has issued its 11th call for papers, and for a change it will explicitly focus on unit processes (and new materials) while continuing to cover the leading edge of integration. The main deadline for paper submissions has now passed, but a limited number of late papers will be accepted until April 11th. The shift in emphasis toward covering unit processes is due to the divergence of integration options moving forward.

Manufacturing ICs on silicon wafers is very complex; hundreds of “unit process” steps (e.g., clean, inspection, etch, deposition, etc) are combined into dozens of “integrated process modules” to form functional structures. One integrated process module may form high-performance transistors, another module forms contacts to transistors, and yet another module forms interconnects between contacts. Many of the unit process steps are copied between modules, and thus has it been since the 1960s.

During the last twenty years, the digital CMOS shrink has been the one process integration direction uniting all the different unit processes under development. The set of requirements for the next node/generation of digital CMOS was always the most challenging for equipment manufacturers working on unit processes. However, starting with the 45nm node, the integration of unit processes has become so complex that there is no one obvious solution for all fabs.

Dr. Thomas Caulfield, EVP of sales, marketing, and customer service for Novellus Systems and former technology executive with IBM, talked with WaferNEWS about the changes in the development of unit-processes in the industry. “As an industry becomes commoditized, how to you differentiate? You either have more efficient design, or more efficient unit processes that allow you to get more productivity or functionality out of the manufacturing. So the last thing you want is the same integrated process,” explained Caulfield. With the leading-edge of IC manufacturing ever increasing in complexity, the productivity of tools used in the fab must increase just to keep costs the same.

Consider the process module to form contacts as an example of integration. Today, the formation of advanced contacts requires something like the following sequence of unit processes:

1) CVD of a blanket dielectric layer,
2) Thermal treatment to stabilize/planarize,
3) Metrology to inspect the layer,
4) Photoresist mask spin-on and bake,
5) Lithography to form initial openings,
6) Treatment to shrink the opening,
7) Metrology to inspect the photoresist,
8) Etch of the dielectric through the mask,
9) Strip/Ash the remaining photoresist,
10) Clean/Treat the dielectric openings,
11) Metrology to inspect openings,
12) Deposit metal barrier layer,
13) Deposit metal for contact,
14) CMP of metal layers, and
15) Metrology to inspect contacts.

Each of these steps has sub-steps too.

In the past, major developments could be described and documented at the integrated process module level, allowing much of the unit process details to be IP secrets. The amazing innovation that enabled digital CMOS shrinks is now pushing against limits of atoms and wavelengths of light, and it now seems clear that further pushes will be ever more expensive. Fabs will also work to integrate analog, RF circuitry, integrated passives, and 3D packages using essentially the same unit processes. “It’s no longer Moore’s Law one-size-fits-all with all the focus on the next generation technology,” explained Caulfield.

Since the integrated process details are now quite sensitive, technologists are relatively more able to talk about developments in unit processes. From an equipment supplier perspective, of course, unit process development does not occur in isolation. “You develop a process capability because you have an application and market in mind,” explains Caulfield. “It’s not that we don’t keep doing that, but today we find customers using the same unit processes in novel ways.”

EDN’s Ron Wilson recently blogged about the IITC call-for-papers and the ramifications of unit process development for IC designers. He considers that porting a physical design from one fab to another may soon require significant inputs from equipment manufacturers, but it is highly unlikely that designers will ever have to talk to OEMs about GDSII files. Using the example of the contact module, the variations in the geometry of the metal contact plug are due to the interdependencies between the different unit processes. Sometimes the source of a structural variation can be easily identified as one unit process, but more often it is impossible to separate out which of the unit processes were to blame. If the diameter of the contact is too large, was the resist overexposed, or was the dielectric overetched?

In addition to the complexity that can be seen in final device structures on the atomic-scale, there are many sacrificial thin-film layers and other “hidden” unit processes within the integrated flow. “It’s funny to watch people debate how something was done based on the data from reverse engineering a final chip,” commented Caulfield. “There’s just no way to conclusively determine the process sequence afterwards with so many sacrificial steps in the integration scheme.”

For example, Novellus sells a pseudo-ALD dielectric tool that forms what they call a pulsed-deposition layer (PDL). Some DRAM fabs use a sacrificial dielectric which they remove with a wet etch, and for this integration scheme the PDL provides no advantage. However, other DRAM fabs use CMP to remove the equivalent sacrificial dielectric, and for them the PDL provides an advantage. The reasons for choosing one integration approach over another are very complex. “People are leveraging unit processes in different ways to try to get the best results while going to higher density,” explained Caulfield. “Productivity or manufacturability differentiation through proprietary integration schemes is the goal—and there are many ways to skin the cat—that provides competitive advantage.”

OEMs have always sold tools that perform basic unit processes, and fabs have always fine-tuned unit processes for integration into modules. The only fundamental change now is that fabs must manage extreme complexity at the same time that most chips have become commodities. “It’s a big problem that the industry is adding manufacturing complexity at the same time that chips are becoming commoditized,” expressed Caulfield. “If you’re not on a curve to take cost out of running a manufacturing tool, then you’ll become the problem that gets worked out of the equation next.”

—E.K.

Labels: CMOS, IITC, integration, OEM, PDL, process, unit

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080211: IITC process units and integration

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