Ed’s Threads 080225
Musings by Ed Korczynski on February 25, 2008

Interconnect technology mature
On-chip interconnects made primarily of copper metal insulated with SiOC low-k dielectric material are the current state-of-the-art for the commercial IC manufacturing industry. A report from the TECHCET Group quantifies the materials that are forecasted to be needed to form interconnects for 65nm to 32nm node ICs. Except for some new barrier layers, the only major change on the interconnect horizon is the use of pores or air-gaps in the dielectric material to get to ultra low-k (ULK, a.k.a. extreme low-k or ELK).

Though carbon nano-tubes (CNT) have been considered as new conductors, and self-assembled dielectrics have also been investigated, commercial IC fabs are necessarily slow to change proven technologies, and so it is almost certain that these newer approaches will not be used for commercial IC manufacturing anytime soon.

From first principles and reasonable modeling, we know that Cu is not the ultimate electrical conductor, but lacking room-temperature superconductors and ways to form dense arrays of metallic CNTs, the only near-term solution is to use more and more copper layers as a method of dealing with higher resistance copper in smaller lines. With Cu pushed to the limits, it is axiomatic that current density inside minimum pitch lines is huge such that electromigration induced reliability problems are inherent.

Cu lines in advanced dual-damascene interconnects are already complex structures, with barrier layers to prevent Cu diffusion into low-k dielectrics. An ideal Cu barrier inhibits electromigration, though any barrier is more resistive than the Cu itself, so it should be as thin as possible to minimize resistivity without allowing for Cu diffusion. For the 32nm node, Copper Manganese (CuMn) and Ruthenium barriers have been investigated, in part due to the integration advantage of being able to electro-plate Cu directly on either barrier without the need for a PVD Cu “seed” deposition. If CuMn is used, then some of the Mn diffuses to the surface of the Cu during metal anneal, and removing this surface Mn during the CMP step results in lower via resistance due to a direct Cu-to-Cu bond.

For cap layers, silicon nitride has been used at ≥90 nm, but it has a rather high dielectric constant of ~7, so SiCN with a dielectric constant of ~5 has been used at 65nm. For 32nm the most likely capping barrier may be CuSiN—formed by reacting the post-CMP Cu with SiH4 and NH3—or CoWP.

Dielectrics technology has never met the wishes of the ITRS for a different material for each node. With the k-value stuck at ~2.7 for a blanket SiOC film, the only practical solution to lower k has been to substitute “air” (a low-pressure vacuum, really) as part of the dielectric material. The air can be in random zero-dimensional “pore” (or nanopore) structures in the material, which may be formed by sublimating the homogeneously-nucleated 2nd-phase of a deposited blanket film. The air can be in random or ordered one-dimensional “air columns” in the material, as shown by Edelstein et al. at IBM. The air can also be in patterned two- and three-dimensional “air-gaps” formed by many different process flows, as shown by Hoofman et al. at Philips/NXP.

Conformal dielectric CVD processes can also be tuned to automatically form air-gaps between lines—known as “key-holes” or “bread-loaves” due to the characteristic shape of the gap when viewed in cross-section—for metal line spaces of a certain pitch. Standard dielectric CVD processes are tuned to avoid air-gaps in random line spaces so that gaps do not appear spontaneously in some portions of a random IC design. Key-hole air-gaps as desired dielectric structures were first reported by Shieh et al. of Stanford in the pages of SST in 1999, and the major limit with their use has been the need to impose design constraints on metal line pitch.

However, it now appears certain that nearly all 32nm node ICs will be made with restricted design rules just so that lithography will work. Likewise, CMP and Etch uniformity specifications at 32nm seem to mandate severe restrictions on geometry and the extensive use of “dummy fill” beyond all precedent. If a design must already deal with such limitations, then why not integrate in key-hole air-gaps by CVD? Alternatively, like IBM or Matsushita, you can use a non-critical lithography masking step and etching to define the air-gap locations independent of line pitch.

Lest we forget, aluminum metal is still used as the on-chip interconnect for some 65nm node memory chips. Proven process technology is replaced only when IC performance mandates a change, and so evolutions happens far more often than revolutions.

—E.K.

Labels: copper, dummy fill, interconnect, low-k, ULK

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080225: Interconnect technology mature

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Ed’s Threads 070608
Musings by Ed Korczynski on June 08, 2007

IITC 2007: Airgaps & chip-stacks
Airgaps and 3D-stacks were the big news from the 10th International Interconnect Technology Conference (IITC) recently held near the San Francisco airport. Two major new materials was presented—IBM showed rhodium (Rh) electro-chemical deposition (ECD) for ≤32nm contact plugs, and Fujitsu showed nano-clustered silicon (NCS) with low k=2.25 for a dielectric—but most new work involves the same materials combined in clever new ways. Airgap technology was covered in four oral presentations, three posters, and countless informal hallway discussions.

Dan Edelstein, IBM Fellow and manager of BEOL technology strategy at Yorktown Heights, NY, gave an invited talk on the many integration challenges for 32nm node interconnects, including resist poisoning from low-k outgassing, low-k damage removal, and the need for improved thin-film interfaces. “We need to keep adding innovation just to stay on the trend-line,” he commented. For example, the industry has historically seen chronically low SiCOH low-k adhesion on SiCHN barrier layers—regardless of equipment, CVD precursor, or plasma preclean—due to a carbon-rich initial deposition. Adding a diverter-valve to the tool allows for stabilized precursor flow before RF power is turned on, which eliminates the carbon-rich deposition and thus solves the adhesion issue. With subtle integration challenges such as these, IBM has chosen to add airgaps as a side-loop with no new materials, tools, or baseline processes. Airgaps drop k by ~35% for any given dielectric material, Edelstein noted, adding that IBM has “shown this on gapped SiOF and low-k SiCOH, and will do it next on ULK porous SiCOH.”

The IBM airgap process both removes and re-deposits some dielectric material, while most airgap approaches for logic chips rely on removal processes alone. The Crolles2Alliance (CEA-Leti, Freescale, NXP, and ST) uses SiO2 at line-levels and a polymer for the via-levels within the dielectric stack, then HF vapor or wet-etch-chemistries to remove the SiO2. NXP and Dow Chemical showed removal of a thermally degradable polymer (TDP) through a CVD SiOC cap layer to make ~30% airgaps at M2 as part of a keff ~2.5 to hit 32nm node specs.

The Crolles2Alliance also showed some of the integration tricks needed to use porous ULK dielectrics at the 32nm node. Different plasmas may seal pore surfaces to provide barrier properties for long-term reliability: CH4 adds C, NH3 substitutes N for C leading toward SiON compositions, and He/H2 plasmas retain near original stoichiometry. Though Cu bulk resistivity is only ~2.2 µOhm-cm, for 60nm line widths it is ~2.9 and increases with reducing widths. CMOS32 uses 50nm Cu line widths for M1, requiring a self-aligned barrier (SAB) <4nm for EM performance, an ALD barrier and thin-Cu seed for filling, and either a CuSiN or CoWP cap layer.

NEC research labs showed that direct ECD of Cu without a Cu-seed layer provides larger grain size and higher Cu(111) orientation. Damascene structures were first sealed with TiN, then either Ta/Cu or Ru layers were deposited. The TiN barrier layer is definitely needed beneath Ru to block Cu diffusion into the dielectric. Ru PVD using DC magnetron sputtering with Ar gas at room temperature produces high orientation of Ru(002). Since Ru(002) is hexagonal-close-packed, it matches well with the preferred Cu(111) face-centered-cubic orientation such that 40%-50% can be grown directly on Ru in dual-damascene structures. Some day, metal line specifications may include not just dimensions and resistivity, but grain orientation and size-distribution too.

Ibaraki U. and Hitachi presented research showing that higher chemical purity leads to lower resistivity in Cu lines. Increasing both the Cu anode purity from 4N to 9N along with the CuSO4·5H2O purity from 3N to 6N reduced line resistance by 21% in 50nm wide lines, with all other process parameters held constant. The high-purity process increased the average grain size from 70 to 74nm, and significantly reduced the oxygen content in the final annealed Cu lines to <1 wt% from the previous 3-4 wt%.

Based on first principles of thermodynamics, an alloy of Cu/Mn can be annealed to result in self-segregation of Mn to the dielectric/Cu barrier. One fundamental advantage of this process is that no barrier is formed at the bottoms of vias, which minimizes resistance. Toshiba’s R&D; group tested self-aligned Mn barriers with 244-via-chain structures and found one-third the resistance compared to Cu vias using the standard Ta barrier.

Georgia Tech and U. of New Mexico researchers showed that a 60% increase in the total number of wire levels is sufficient to account for ~5x increase in the resistivity of wires. Careful routing and a logical hierarchy seem to go a long way, but eventually the industry must get serious about 3D ICs using chip-stacks.

Patrick Leduc of CEA-Leti provided an overview of the main challenges to realizing high density 3D ICs: bonding with ±1µm alignment at T<400°C, Si thinning to <15µm, and through-silicon via (TSV) diameters <3µm. Thermal management issues may not be too difficult—assuming each transistor contributes 0.7W to a 50 W/cm2 average—since bulk silicon acts as an efficient heat spreader and the metal lines conduct well.

Freescale’s Scott Pozder explained that EDA software tools may be the current biggest limitation to 3D integration, since standard tools cannot even account for metal levels on multiple chips. If you explicitly design for 3D, then models show that multiplicative yield-losses can be avoided or eliminated.

There were ~480 conference attendees this year (plus several hundred additional folks running evening supplier-seminars and exhibit booths). Among the attendees with whom I enjoyed discussions were (in alphabetical order) Al Bergendahl, Chris Case, Paul Feeney, Terry Francis, Mike Fury, Xiao Hu Liu, Steven Luce, Satya Nitta, Mike Shapiro, and a special appearance by casually retired Mike Thomas.

—E.K.

Labels: airgap, copper, dual-damascene, IITC, interconnect, low-k, self-aligned barrier, ULK

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070608: IITC2007 airgaps & chip-stacks

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Ed’s Threads 070525
Musings by Ed Korczynski on May 25, 2007

Intel-IBM fab hype-war and truths
It has been said that the first casualty of war is the truth…even more so in a hype-war. An interview appearing on a popular electronics industry Web site is the most recent battlefield in this ongoing hype-war between the world’s semiconductor manufacturing heavyweights. As tradeoffs in fab technology become more fundamental at 45nm nodes and beyond, different companies choose to deploy similar technologies in different ways. The truth is inherently complex and thus a bit complex to describe, and can die under the assault of hype.

Among fundamental choices today we find the following: double-patterned dry or single-patterned wet lithography for critical layer patterning, and use of porous or airgap low-k dielectric for on-chip multi-level interconnects. Intel has chosen double-patterned dry lithography and non-airgap low-k dielectrics. IBM has chosen single-patterned wet-lithography and airgap dielectrics.

As shown by Hoofman, et.al, in the pages of SST last year, there are many different airgap process flows, which can produce many different airgap structures. Airgaps may be complete or partial between lines, and this is one of the more fundamental parameters to consider in integrating the structures into real chips. Thus, airgap1 is not airgap2 (General Semantics suggests the use of “indexing” to remind us of the essential distinctions between members of any conceptual set).

Using “complete airgap” flows and removing all dielectric between lines to achieve the absolute minimum capacitance does indeed create the two general problems articulated by Mark Bohr in the recorded interview: an expensive critical-lithography mask to ensure proper via landings, and copper electromigration sensitivity. However, the IBM flow uses airgaps only in the middle of line spaces while leaving dielectric material on the sidewalls of copper lines.

The IBM airgap process exposes parts of some metal sidewalls during the tricky three-stage gap etch, but the subsequent dielectric CVD process re-coats the exposed sidewall areas prior to “pinching off” the tops of gaps. With adequate sidewall dielectric in place, via landing and electromigration issues can be minimized if not avoided. Intel’s Bohr certainly understands airgap integration issues far better than I do, but because he’s not in a position to comment on how his competitor’s process might work, he accurately and properly expressed Intel’s results in the interview, and the generic disadvantages of approaches not currently taken by Intel.

However, a statement summarizing the interview reads thusly: “Mark Bohr, Intel senior fellow, says his company looked at air-gap technology like IBM recently introduced, and dismissed it as costly and inefficient.” That's a misinterpretation. The truth is that Intel never panned IBM’s airgap technology—Bohr answered a specific question about IBM’s technology with a generic answer about non-IBM technology. Of course, Bohr can very reasonably say that he has no knowledge if IBM’s technology beyond what is muddied in the official press release. Since IBM’s marketing spun the technology truth to the point of grandiose hype, it provides easy opportunity for Intel to comment on the hype instead of the truth. (Incidentally, further information on the general concept of self-assembled nanotechnology for lithographic masking applications can be found in the most recent issue of Microlithography World.)

The IBM hype was that no new lithography is needed. Intel counters that a generic process flow for airgaps requires critical-lithography steps. The truth is that the IBM flow does use an additional lithography step for each airgap level, but it’s non-critical and the mask generation has been automated as a button in the EDA deck. Critical-lithography steps for 45nm node processing can be 10X more expensive than non-critical patterning steps. If the IBM airgap process required critical lithography for each level then it might add 20%-25% to the cost of each chip, but with non-critical lithography it might add only 5%-8%.

For most people in the world who lack experience in fab processes, subtle complexities get lost in translation and details are distorted or lost. The truth about nanometer-era fab processes is that they are all tough to develop with inherent integration trade-offs. With Intel and IBM now going down divergent paths, it’s truly difficult to assess a fab technology “leader” in anything but hype.

— E.K.

Labels: airgap, fab, IBM, IC, Intel, interconnect, low-k, self-assembly, ULK

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070525: Intel-IBM fab hype-war and truths

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Ed’s Threads 070504
Musings by Ed Korczynski on May 04, 2007 (updated June 12, 2007 to correct details of the IBM airgap etch process, which had erroneously referred to the third-step being RIE, when it is wet as confirmed by both D. Edelstein and S. Nitta)

IBM adds airgaps for faster chips
Airgaps have long been considered as structures to increase the speed of on-chip IC interconnects, though no one had developed manufacturing-worthy process flows. Only in the last year have companies such as Philips (now NXP) shown overviews of likely airgap manufacturing processes, though without production commitments. Now IBM has invented a new variation on airgaps that uses a self-assembling polymer mask layer as part of the process flow, and claims this can be a simple drop-in addition that adds only ~1% to chip cost for each dielectric layer gapped. Thus for an advanced multilevel interconnect, a ~5% cost adder should provide 35% faster chips or 15% less power consumption.

Circuit speeds are limited by the dielectric constant (k) of the insulating material surrounding metal lines, so the industry's Roadmap has focused on ever lower k dielectric materials. Unfortunately, materials engineering for a new dielectric material is difficult and expensive, and despite tremendous efforts and many false-starts over the years, the entire world has now settled on SiCOH by CVD as the lone dielectric material (k~3) that provides acceptable cost, yield, and reliability. So-called ultralow-k (ULK, aka “extreme low-k”) films are merely k~3 SiCOH with the addition of ~20%-40% by volume of nanopores to reach k~2.4. More nanopores cannot be added without degrading yield and reliability, so the only practical way to get to k~2 is to incorporate a single large pore with clever processing as an “airgap.”

A multiyear development effort to create a manufacturable airgap process was led by IBM fellow Dan Edelstein, program manager for low-k CVD BEOL, who provided Solid State Technology and WaferNews with exclusive insight into how they achieved these remarkable results. He explained that unlike previously known airgap process flows, the IBM approach starts with a standard dual-damascene copper and SiCOH dielectric process that has been in production for years. Airgaps are formed using a multi-step etch, using a hardmask patterned with either self-assembling monolayers or standard lithography depending upon the geometry of the interconnect.

Unfortunately, IBM's press release touting the airgap achievement is so grossly hyped that it’s caused severe misunderstanding throughout most press reports on this process. The new technique "skips the masking and light-etching process,” says the official release. “Instead IBM scientists discovered the right mix of compounds, which they pour onto a silicon wafer with the wired chip patterns, then bake it.”

In reality, while self-assembly can be used to make an array of nominally 20nm holes by spin-coating and baking, these holes merely pattern the hardmask that is used to etch the gaps into the dielectric, explained Edelstein. A non-critical lithography step is used to block out circuit areas that do not need gaps, he said. The self-assembly layer is not even used to pattern the hardmask used to make airgaps at upper levels of the interconnect. “At some point in the hierarchy it becomes more viable to use lithography instead of self-assembly,” he said.

While IBM doesn't use airgaps for the first level of metal, they could be used at any of the higher levels within the hierarchical interconnect stack, Edelstein noted. “Most chips won’t need air-gaps on all levels, but perhaps on half,” he said.

No matter the level, a special three-step etch process to form gaps with narrow top openings is the key to this process (see figure). “We etch a narrow channel down so it will cap off, then deliberately damage the dielectric and etch it so it looks like a balloon,” he explained. “You have a big gap with a drop in capacitance and then a small slot that gets pinched off.”

Starting with dual-damascene copper lines/vias and SiCOH single-phase dielectric, the essential IBM airgap process flow is as follows:

1) Deposit hardmask;
2) Spin-coat an imaging layer; either special new diblock polymer or standard photoresist;
3) Create holes using either the self-assembly properties of the diblock or standard lithography;
4) Block out circuit areas to not be etched using non-critical photolithography;
5) Transfer holes from the imaging layer to the hardmask;
6) Etch three-step sequence—first an anisotropic RIE to form deep openings into SiCOH, then plasma damage of the column sidewalls, then isotropic wet etch to remove most of the remaining SiCOH underneath the hardmask;
7) Strip hardmask; and
8) PECVD of the next SiCOH dielectric level to cap the gaps with a classic “pinch-off” shape.

Since the self-assembling mask layer is not aligned to the underlying interconnect structures, and since the block-out mask is “non-critical” to save costs, the hardmask will inevitably expose the tops and sides of some metal lines to RIE. Consequently, the SiCOH etch chemistry needs to have excellent selectivity so as to not attack copper and any metallic barrier layers. Edelstein says that they’ve been able to work with standard gas precursors for this critical RIE step.

The new airgap process is an optional loop off of the standard flow, so designers can choose to use airgaps at any of the levels in the on-chip interconnect hierarchy—and IBM also has developed an automated algorithm for making the block-out mask. “As a customer you can turn on the air-gap option for any level on any chip. We can put the gaps in independent of any incoming design,” Edelstein told WaferNEWS. The ability to add air-gaps as a “drop-in” to an existing on-chip interconnect process flow minimizes risks, and explains the company’s confidence that this flow will be used in manufacturing by 2009.

While the diblock polymer is only one part of this airgap process, it is a significant addition. Chemists at IBM Almaden Research reportedly developed this material for broad applications in fabs—it’s like a standard photoresist in terms of handling and dispensing, it has a wide process window, and IBM has detected no shelf-life problems for up to one year.

Using self-assembly in coordination with lithography opens up new possibilities in general for integrated process flows, so look for news of additional applications in coming years. “We hope that we can use directed self-assembly to get to other device features,” said Edelstein. “This is just the tip of the iceberg.”

— E.K.

Labels: airgap, fab, IBM, IC, interconnect, low-k, self-assebly, ULK

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070504: IBM add airgaps for faster chips

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