Ed’s Threads 080414
Musings by Ed Korczynski on April 14, 2008

Energy Costs mean externalities matter
What do the words “Energy” and “Costs” have to do with materials considerations in 2008? The most recent issue of the Materials Research Society (MRS) Bulletin has just been released and it’s a special issue devoted to exploring all aspects—including costs—of materials science and engineering for energy. Many fine companies like Applied Materials sponsored the issue being made free to the public at the MRS website, and at minimum all adults should read “The Economics of Energy Options” by Lester B. Lave of Carnegie-Mellon University.

“Energy” is an amazing word. Normally defined as the “ability to do work,” we might define “work” as the “ability of use energy”…so the more you study it the more you find circular logic. To further confuse things, we talk about “potential” energy and “kinetic” energy and “random” energy and “surface” energy and “renewable” energy too. Because the term has vague and overlapping definitions, people tend to use the term as they see fit without considering how other people might be using the term.

“Costs” seems like a simple word until you consider “my” cost versus “our” cost…which is the simple way of framing the discussion of economic “externality” wherein I profit by making you pay for some of my cost. ROHS is an example of a topic that is clearly foolish or clearly wise depending upon where you draw the line for the limits of your system: if you only consider your system to be electronics design, manufacturing, distribution, and sales then eliminating lead from PCBs just adds cost and risk. If, however, you consider your system to be society as a whole and include electronics recycling, landfill maintenance, and human health care expenses then eliminating hazardous substances from electronics should reduce overall costs.

“Many of the energy decisions that U.S. residents currently make are conditioned by the subsidies that energy has enjoyed. Until the 1970s, there were few rules requiring companies to abate the air pollution emissions from burning fossil fuels. Fuel was sufficiently abundant that prices were extremely low. Coal and oil were extracted with little thought or care for environmental quality,” says Lave. “As a result, huge social costs were incurred through environmental degradation and the resulting ill health.” The U.S. Environmental Protection Agency (EPA), in a study titled “The Benefits and Costs of the Clean Air Act, 1970 to 1990,” estimated that abating air pollution had benefits of $22 trillion compared to abatement costs of $523 billion; thus, benefits were more than 40 times greater than costs.

“The costs of U.S. foreign and defense policies to secure large amounts of inexpensive petroleum have not been charged to the imported energy. Consumers made decisions on what car to buy, what size residence to buy, and what temperature to set the thermostat on the basis of artificially lowered prices. Subsidizing a product encourages its use. Thus, the energy policy of the United States has encouraged energy use beyond what it would have been if the price had reflected full social cost,” concluded Lave.

I was born in Detroit (“Motor City”) and still enjoy motor sports, and I’m more than willing to pay $5/gal for gasoline to fuel my fun machines. From first principles of power-to-weight, electric motors should out-torque and out-fun internal combustion engines, but historic batteries had limited life and range and so for 100 years we have been waiting for convenient electric cars to arrive…

Philips in The Netherlands is leading research into new storage technologies for electricity, using 3D trenches in silicon to massively increase the surface area of solid-state rechargeable batteries. This technology derived from silicon IC STI etching could be used in small 3D integrated electronics systems, or potentially even in automobiles.

Lave’s article mentions the need for improved battery technology as part of our desired energy future. “A battery that could power a vehicle for 30–40 miles (48–64 km) and be recharged from an electricity outlet would save about two-thirds of gasoline use. Because only about 2% of electricity is generated from petroleum, if all automobiles and light trucks were plug-in hybrids, more than one-half of oil imports could be eliminated."

The whole debate over the “true” costs of energy centers on where we draw the line on our system, and this is clearly seen in the debate over “solar subsidies.” What is the grid cost of electricity where you live? How much is subsidized directly or indirectly by your government? Do you have to pay a huge upfront cost for your home or are major infrastructure investments absorbed by someone else and you just pay per month? All of these questions relate to the issue of government subsidies to encourage private investment in photovoltaic solar panels.

Meanwhile, Southern California Edison (SCE) announced that recent advances in solar technology combined with a new five-year mega-scale investments allows for costs to drop by one-half. “This project will turn two square miles of unused commercial rooftops into advanced solar generating stations,” said John E. Bryson, Edison International chairman and CEO. “We hope to have the first solar rooftops in service by August. The sunlight power will be available to meet our largest challenge – peak load demands on the hottest days.”

You can put it in my backyard.

—E.K.

Labels: battery, costs, energy, externality, materials research, PV, solar

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080414: Energy Costs mean externalities matter

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Ed’s Threads 20080331
Musings by Ed Korczynski on March 31, 2008

MRS meeting covers nanostuff and microthings
Over 4000 researchers were in San Francisco last week for the annual Materials Research Society (MRS) spring meeting, to discuss advances in materials for electronics, energy, health, and transportation. Over 40 technical session run in parallel, with >10 sessions of interest to the semiconductor manufacturing industry at any given time. Theory and results for new IC memory cells, extensions of CMOS logic, and future quantum-dots and nano-rods were shown. Graphene still seems like a possible replacement for silicon in ICs.

In his Kavli plenary lecture in nanoscience, Prof. A. Paul Alivisatos of UC-Berkeley described recent work by his group and others on transformations in nanocrystals. Chemical transformations can be used to obtain complex nanocrystalline structures though sequential chemical operations. In an example, CdSe reacted with Ag+ to form Ag2Se which could then be combined with Cd2+ to completely reverse back to CdSe, while the volume of the nanoparticle was completely preserved. Such cation exchanges can occur in semiconductor nanorods and hollow spheres with shape preservation, but when shapes do transform their final forms are currently difficult to predict.

Much of the new materials work is targeted toward finding nanoscale structures which can switch between two measurable states to function as memory cells. Two of the newer random-access memory (RAM) cell types under development are phase-change RAM (PRAM) and resistive RAM (ReRAM). With Numonyx now officially launched to commercialize PRAM along with Flash, there were many papers looking at manufacturing process flows to optimize the deposition and programming of the antimony-telluride (SbTe) family of “calcogenide” materials which undergo thermally-assisted transitions between crystalline and amorphous phases. Independent of the MRS meeting, materials supplier ATMI recently announced co-development plans with Ovonyx for calcogenide CVD precursors.

ReRAM using metal-oxides as switching elements comes in two fundamentally different variations: one-time programmable through the growth of nano-metallic-filaments, and reversible through ionic transport between electrodes. ReRAM materials may be used in PRAM-like cells, or also used as the switching element in cross-bar architecture arrays. HP Labs, US NIST, and Hokkaido University all showed advances in hybrid circuits built using cross-bar arrays.

For extensions of CMOS logic, with a somewhat clear path forward in new materials for high-k and metal gates, a lot of research now centers on doping technologies. G. Lansbergen et al. (B3.7) from TU Delft (The Netherlands) along with Purdue (USA), University of Melbourne (Australia), IMEC (Belgium), and Caltech (USA) showed the ability to work with a single Arsenic dopant atom in a p-MOS finFET; their experiments represent the first evidence of the ability to engineer the quantum state of a single-donor electron by surface gate control. While single-ion doping is way beyond today’s fab specs, more precise control is needed for the placement of often <100 atoms for channels and contacts.

Wilfried Vandervorst of IMEC showed that Laser Spike Anneal (LSA) which is essentially “diffusion-less” calls for re-integration from prior rapid-thermal annealing (RTA) schemes where lateral diffusion is significant. Due to the very low thermal budgets needed to form ultra-shallow junctions (USJ), LSA is more subject to pocket dopant fluctuations than spike anneals. Random dopant fluctuations must be controlled, along with structural variations on gate cross-sections which appear as undercuts and footing. LSA helps equivalent oxide thickness (EOT) scaling for gate dielectrics by elimination of a 2-3Å thick re-growth layer. However, to ensure reliability in gate stacks, an RTA step can be added after LSA to improve the situation somewhat. Looking forward to embedded SiGe, LSA so far induces junction leakage and defects gliding along certain crystalline planes which unfortunately relaxes desired strain. LSA for embedded SiC, however, avoids SiC relaxation which improves the strain retention in nMOS. Gate profile control is critical for diffusion-less USJ, which may mean gate-last integation schemes will be easier to integrate.

Karuppanan Sheker, of SemEquip, presented on how to use cluster-carbon implants to improve the Si:C layer formation. There is ~2% limit to how much C can be substituted in silicon lattice. At the VLSI Technology Symposium 2007, IBM showed [C]sub of 1.65% with mono-atomic C implants and pre-amorphizing implants (PAI). Using clustered carbon eliminates the need for the PAI and provides [C]sub >2%. The source is two benzene rings in the form of C14H14, which upon striking a silicon crystal in the 6-10keV implant energy range automatically induces amorphization with depth of 20nm-40nm. The greater the amorphous layer thickness the higher the percentage C which can be substitutionally incorporated.

Newer finFET architectures, which may first be used for SRAM arrays, require unique integration flows. Mark van Dal, NXP-TSMC Research Center, showed that when implants into fins amorphized the silicon material, the re-crystallization in complex fin shapes results in scattering and other sources of variability. The exact reason for the device degradation is not known, but using either BF2 or B+Ge implants (both of which induce amorphization) result in more transistor variability. At fin widths of 1µm there is no difference, but for fins <0.1µm wide the effect is clearly seen. When non-amorphizing B implants are used, no device performance degradation is observed.

— E.K.

Labels: CMOS, finFET, graphene, materials research, nano, PRAM, ReRAM

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080331: MRS meeting covers nanostuff and microthings

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Ed’s Threads 080324
Musings by Ed Korczynski on March 24, 2008

Etching new IC materials at 32 and 22nm
Silicon Valley was once the center of the silicon-based IC manufacturing world, and though IC fabs are now located globally the valley maintains momentum as the center of IC R&D. The North-California Chapter of the American Vacuum Society (NCCAVS) still runs regular users groups on important industry topics, and the plasma-etch users group (PEUG) meeting on March 13th featured presentations by IBM and Applied Materials on advanced etch processes for 32nm and 22nm node ICs.

Nicolas Gani, of the silicon etch division of Applied Materials, presented on work done in collaboration with IBM on plasma etching for gate-stacks for 45nm and 32nm node CMOS transistors. Since the stack is composed of multiple materials, different single-wafer etch chambers for different etch conditions are ideally clustered together into a single tool. One chamber is designed for poly-silicon etching at relatively low temperature, while another chamber is designed for high-k/MG material removal at relatively higher temperatures of 130-220°C.

High-k materials such as HfO2 demonstrate etch rates in Cl2 plasmas with zero bias power that increase linearly by ~4X over the 100-200°C range, though rate-studies indicate there is some ionization component to the etch even without bias. High source-power can actually induce polymerization which shuts down the HfO2 etching. Using 20 W bias allows for 100s Å/min etch rate. One of the key issues in tuning etch processes is the elimination of any “foot” at the bottom cross-section of line-stacks. Applied Materials has shown that etching at >200°C leaves <1nm of a foot, while a 3-4nm foot is seen at <100°C. The temperature control is modest since for etching at greater than ~150°C the reaction is surface limited so that uniformity across the wafer is guaranteed even with an ESC only controlling to ~5°C.

Nicolas Fuller of IBM Research talked about plasma etching challenges for 22nm node etching, with most of the work done at Yorktown Heights, though unit process work was also done at East Fishkill and Albany. Device options for 22nm include finFETs and SOI, and both structures create unique etch challenges. “The fin itself can charge,” explained Fuller. “It may have a hardmask, and charging during the etch can produce an ion steering effect that induces greater etch rate in the middle of structures.” Going to 3D represents a challenge, and—as per the classic wisdom—also an opportunity. “Here charging potentially represents an advantage. You might want to charge the metal gate to induce ion steering to minimize footing,” claimed Fuller.

As complex as today’s leading edge 45nm production may be, halving the scale seems like it could be an order of magnitude more difficult. For sidewall image transfer (SIT) to get the types of structures at 22nm node fin pitches we may need some manner of atomic-level etching (ALE) to conceptually match ALD. New line-edge roughness (LER) and line-width roughness (LWR) issues will be induced by multiple exposures and multiple etches anticipated in 22nm integrated double-patterning process flows.

IBM shows us that after lithography to form 24nm wide lines at 80nm pitch there was 2.6/4.9 LER/LWR (3 sigma); and best lab results were 1.4/2.3 has been achieved with multistage etches of organic/inorganic materials as masks using boutique combinations of e-beam and optical litho. Plasma etch work ongoing at Albany now suggest that high-frequency plasma parameters are the main factors which must be controlled to minimize LER/LWR. There’s barely any CD error budget left, and etch has to share the vanishingly few nanometers with lithography and metrology and deposition. Hold tight.

—E.K.

Labels: 22nm, 32nm, etch, LER, materials research, NCCAVS, PEUG

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080324: Etching new IC materials at 32 and 22nm

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Labels: electronic, LED, materials research, packaging, photovoltaic, PV, solar

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080121: SMC highlights PV, LED, and packaging materials

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Ed’s Threads 070803
Musings by Ed Korczynski on August 03, 2007

Intermolecular blazes new trails for labs and fabs
Intermolecular, which officially decloaked at this year's SEMICON West, has taken high-productivity combinatorial (HPC) technology from a Symyx license and added test-chips/parametric-testers and informatics software to revolutionize the way new materials technology is developed in labs and deployed in high-volume fabs. Intermolecular works to provide faster time-to-market, at lower cost, and lower technology risk. Symyx’s license to Intermolecular includes the IC space, FPDs, bio-chips, MEMS, and any combination of active and passive circuit elements on a planar substrate.

Subtle differences between R&D; and process chambers mean that subtle materials properties can change final device results. Thus, while basic materials research can be safely done on R&D; tools, unit process development and subsequent process integration have to occur with high-volume manufacturing tools. These production systems are typically not flexible, and changing materials and parameters can be so slow that an experiment can take from an hour to a day to run.

“The majority of the $20+ billion in annual technology development for the industry is spent in process integration,” said Intermolecular founder and CEO David Lazovsky, in an on-site interview with WaferNEWS. Thus, Intermolecular’s ~700 applied-for patents deal with the three basic technology development stages of the industry:

-- Materials research, performing 500 experiments/wafer of basic materials properties;
-- Unit process development, reproducing 100s of processes/wafer on customer production wafers; and
-- Process integration, doing 10s of experiments/day that output parametric/wafer-level reliability (WLR) data.

The company has invested substantial resources to increase staff up to ~70 people with backgrounds in process, equipment, test-chip design, software, and surface chemistry. Investment in lab space and hardware has led to unique tools to process full wafers and also rectangular silicon “coupons,” parametric testers, and an Applied Materials’ Endura PVD tool that allows for correlation experiments between combinatorial modeling and high-volume production tool performance.

“Gradients are terrific if you’re just looking for materials properties. But at the device level for the IC industry, having a gradient across the device won’t be of any use,” explained Lazovsky. "What we enable is discretized processing so you have control over an area like you would in a high-volume processing system."

Using high-volume production tools for development has always been a bottleneck, but with the plethora of new materials interactions to be tested for 32nm node IC manufacturing, there’s a tipping point. What's needed is far more than a mere doubling or trebling of efficiency -- we need orders of magnitude faster results.

Intermolecular's Tempus F-20 tool performs fluids experiments using arrays of beakers/pipettes and silicon coupons for early and middle stage screening experiments with hundreds of splits simultaneously. The Tempus F-30 (used for latter stages of screening) performs fluids experiments on full 300mm wafers, using an array of tiny (~1-in. dia) circular chambers with Teflon seals to provide 28 different experimental splits across a wafer (see figure below).


For example, with parallelism a full wafer can be processed through the following four sequential wet steps in just four minutes using a parallel processing station and an adjacent blanket processing station:
-- Pre-clean,
-- Self-assembled monolayer dep.,
-- E-less cobalt dep., and
-- Post-clean.

For integration work, a customer (or a customer’s customer) provides patterned wafers pulled from a fab line. After combinatorial depositions, parametric testers can extract device data from each of the 28 discrete splits.

The self-assembled monolayer is a molecular masking layer (MML), a novel molecule synthesized specifically to bond to various low-k dielectric films, and provide a uniform top surface for an electroless deposition. The MML was synthesized after 7635 experiments with 60 molecules ran on 25 wafers in 5 weeks…and at the end of electrical tests they found two molecules that had some of the right properties. One of these was the basis for synthesizing a new precursor for a materials supplier customer that is a low viscosity liquid at room temperature.

As another example, Intermolecular helped a leading Taiwanese foundry develop a wider process window for interconnect cleans for the transition from the 65nm to the 45nm nodes.

Fluids-based processing hardware is available for sale and license along with support. PVD tools are internally developed for collaborative development programs, and will be productized for sale as hardware like the fluids tool. ALD is on the company's roadmap.

Since Intermolecular focuses on integration, investments in test-chip design software and parametric test hardware allow for sophisticated optimizations of circuit functions. Working with partially processed wafers, Intermolecular rapidly screened >12,000 sets of flash memory cells using PVD, followed by additional screening to optimize the read/write pulses to match the properties of the new cell. “So there are combinatorial methods used to develop the materials system, and there’re also combinatorial methods used in how you operate the cell. That’s part of the solutions space, and it’s non-trivial,” commented EVP of business development Gustavo Pinto.

Intermolecular seems to have found a truly new and powerful methodology to integrate new materials into advanced ICs. With the ability to do deposition experiments on at least 28 discrete areas of a wafer and then test and extract productive information from massive data dumps, you can get a lot of work done. Rarely is the use of clichés like “paradigm shift” or “revolutionary” justified…but this might well be one of those rare cases.

—E.K.

Labels: combinatorial, development, HPC, materials research

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070803: Intermolecular blazes new trails for labs and fabs

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Ed’s Threads 070413
Musings by Ed Korczynski on April 13, 2007

MRS meeting specs the future
The Materials Research Society (MRS) spring meeting was in San Francisco April 9-13, and the near- and far-term possibilities for process technology in our industry were presented to a record numbers of attendees. Researchers showed results from the world’s leading labs for electronic materials development: CMOS high-k gate dielectrics, nano-imprint lithography, organic semiconductors, quantum dots, and nano-tubes. It’s like sipping from a firehose, unless you’re interested in just one of the 36 parallel sessions.

Sachin Joshi of UT-Austin showed that hybrid-orientation technology (HOT) silicon wafers based on the MEMC direct silicon bonding (DSB) approach contain inherent defect-rich junctions between orientations. Shallow-trench isolation (STI) regions 60-140nm wide may be used to eliminate these defects, though this seriously limits circuit density, he pointed out. Non-silicon channels will probably also limit density, so their use will probably be limited to RF and mixed-signal applications in small portions of chips.

Arief Budiman from Stanford analyzed the grain orientation in submicron damascene copper lines using the synchrotron x-ray beam from the ALS Berkeley Lab. This very bright x-ray source and submicron spot-size (0.8 x 0.8µm) allows for resolution of crystal bending/stress as well as the dislocation density. Starting with large single grains spanning across the width of the line (“bamboo structure”), Budiman’s group observed clear directionality of EM-induced plasticity and thus the orientation of slip-planes. They found that <112> orientations were most susceptible to plastic deformation, so any grains with such orientations that line up with the induced EM-stress will deform. Grain orientation controls plasticity, which in turn influences EM degradation mechanisms and circuit reliability.

An analysis of the influence of microstructure on void formation in failed copper interconnects, from Intel's Sadasivan Shankar, revealed that voids first nucleate at triple-boundaries caused by stress-induced de-cohesion at copper interfaces. These voids can be easily pinned by a grain boundary, which provides a fast diffusion path for the void to grow across the width of a line or via. “It almost unzips the grain-boundary,” he commented. A 2D model developed with Brown and UT-Austin accounts for current flow and stress, diffusion along surfaces and interfaces, void migration, and the interaction of voids and grain boundaries.

Duane Boning, the MIT professor who created one of the first useful pattern-density step-height CMP models in the 1990s, showed progress on new physically based models. By explicitly including pad properties—elastic response (including lateral coupling across the pad), slurry transport, and average asperities—he showed how chip-scale uniformity can now be predicted.

Roland Rzehak of Qimonda in Dresden, Germany, provided both an overview and details of inexplicable CMP removal-rate variations using ceria-slurries. A counter-intuitive “slow start phenomena” slows the removal rate for the first minute of pattern planarization to be ~2.5X lower than that for blanket films. Ceria particles may initially adsorb in trenches to take some of the pressure load. However, Qimonda observes additional non-uniformities implying influences of pattern pitch, the pad material, and possibly effects from chemical additives to the slurry.

MRS meetings also cover wilder technologies like superconductors, neuro-prosthetic interfaces, and “the nature of design using nature’s portfolio” like the self-assembly of sea-shells or the nano-hairs of gecko feet. Materials scientists and engineers continue to explore the structure-property relationships of the physical world, and confirm that there is indeed “still plenty of room at the bottom.”

— E.K.

Labels: electronics, materials research, modeling, nano, self-assembly, silicon

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070413: MRS meeting specs the future

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