Ed’s Threads 070824
Musings by Ed Korczynski on August 24, 2007

Intel finds signs of heterogeneous life after silicon
With CMOS circuits using silicon channels running into performance limitations, doping with germanium and straining the lattice have already been used to push the limits. The limits of silicon remain, though, and so compound semiconductors are again under consideration as building blocks for mainstream ICs—this time integrated on top of 300mm silicon wafers.

The first solid-state transistors were built with germanium (Ge), but Ge crystals do not grow a nice surface-passivating oxide as do silicon crystals, and the oxide is vital to prevent surface defects that would otherwise kill performance. Grown silicon oxide has been the heart of cost-effective high-volume IC production for over 40 years. Even high-k (HK) gate dielectrics based on hafnium-oxides will typically be used on top of a grown and partially etched-back silicon oxide layer.

What comes after high-k and metal-gates (HK+MG)? Heterogeneous integration of compound semiconductors will completely replace the silicon channel. Silicon wafers would still be used, but only as physical supports for different NMOS and PMOS transistor materials. The new channel materials will be deposited and/or grown using technologies such as metal-organic CVD (MOCVD), solid-phase epitaxy (SPE), and spike/flash anneals.

Though HK+MG has been spun as the biggest change in 40 years, when compound semiconductors are integrated with silicon it will be a far greater integration challenge for it will require an even greater number of new materials. Now Intel researchers have reported passing a milestone along the road many travel to heterogeneous integration: integrated superior device performance.

This summer, Intel researchers achieved success at fabricating high performance devices using both indium antimony (InSb) and indium gallium arsenide (InGaAs) channels, and in each case they perform as well as their counterparts on GaAs wafers. On their internal blog, they show curves for the performance of both types of devices, with individual transistors both higher performing and consuming less power than equivalently sized silicon devices.

Mike Mayberry, Intel’s director of components research, has articulated five general areas of research and develop needed to create a competitive commercial heterogeneous semiconductor fab technology:
1) put compound semiconductors on silicon wafers,
2) find different high-k dielectrics for the gates,
3) develop PMOS materials to go with known NMOS,
4) develop enhancement-mode devices instead of depletion-mode, and
5) “Make them small enough to compete with silicon transistor densities.”

The last is the tricky part. These circuits are conceived of as being possible at or past the 22nm node, so that means high-yielding dense 32nm and likely 22nm CMOS circuits will already be in production using strained SiGe. Heterogeneous circuits will have to compete with Si/SiGe chips on price, so transistor packing density will be crucial.

By the time InSb and InGaAs could be integrated on silicon wafers, finFETs should also be options along with planar transistor structures. In an email exchange with me after his initial blog posting, Mayberry answered some questions relating to finFETs as possible structures for heterogeneous integration. “It is possible that in the timeframe we’re discussing that trigate structures could be a strong candidate and thus, that builds pressure to find a vertical solution for III-V,” he confirmed, but he admitted that, “we do not as yet have a solution to that problem.”

If finFETs are used, new metal alloys will need to be developed to be able to form minimal resistance electrical contacts to these new materials. Even if planar structures are used, the contacts will almost certainly be to the channel material instead of silicon to avoid the need for a >5nm transition zone from material to material that would otherwise limit packing density. Due to the need for this transition layer in planar devices with silicon contacts, and the performance advantages to a reduced number of boundary layers, it seems likely that metal contacts will be direct to the new compound semiconductor materials.

In my email exchange with Mayberry, he confirmed only that “we have not decided how to make electrical contact for those future devices.” One thing he knows—and will let us know—is that for Intel’s current work, SOI would just get in the way and everything is grown on bulk silicon wafers.

This is all starting to get into some serious materials engineering. Mayberry’s blog pre-announces that they will show enhancement-mode device results using these materials at IEDM this December. Since these newest devices will be “normally off” they should result in minimal leakage and reduced power-consumption for circuits. We can almost certainly expect unexpected subtle second-order integration challenges with all of these new materials, with the semiconductor industry now moving into “interesting times.”

–E.K.

Labels: compound semiconductor, heterogeneous, IC, integration, Intel

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070824: Intel finds signs of heterogeneous life after silicon

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Ed’s Threads 070817
Musings by Ed Korczynski on August 17, 2007

FEI Phenom - SEM for the people

FEI has been supplying Scanning electron microscopes (SEM) to the semiconductor industry to help inspect ever smaller circuit-elements during the decades of the shrink. Now the miniaturization in electronics enabled by SEMs has been paired with miniaturized hardware to create a small revolution in microscopy. The company's new Phenom electron microscope, the size of a large coffee maker (Fig. 1) plus a small below-table vacuum pump, requires no external vibration isolation, can load a sample in <30 seconds, and costs <$80K.

Information is power, but it’s got to be “productive information” to be useful in production. Knowing what you’ve got is critical, so cost-effective metrology and inspection tools are essential for the operation of labs as well as fabs. SEMs provide essential information from R&D; to manufacturing quality control, but they are generally slow and sensitive instruments. It takes a skilled technician many minutes to load and focus samples in expensive tools, such that “SEM time” is a common bottleneck in R&D.;
The first SEM was developed in 1961 (Fig. 2). The electronics have shunk over the decades, and analysis capabilities such as energy-dispersive X-ray microanalysis have evolved, but the basic layout and size of the electron column and vacuum chamber have remained somewhat constant. Now FEI has shown that throwing out the old playbook and starting from scratch can produce a revolution in inspection tools.

Developed for broad ubiquitous applications in science and engineering after an “ah-ha” flash of insight a few years ago, the Phenom is the first commercial tool from FEI to take advantage of a real hardware miniaturization revolution.

By shrinking the electron column down so that it actually fits in the palm of your hand (Fig. 3),



and mating it to a miniscule vacuum-chamber and sample-holder cup (Fig. 4),





the combined small mass can be so rigidly coupled that it floats free from external vibrations.

At SEMICON West this year, the company showed a working unit on top of a cheap display table. I knocked on the sides of the unit and could see the tool’s outer skin vibrating while the image from the sample inside remained rock solid (Fig. 5).
The adjacent image was taken by me as the SEM operator after just three minutes of training. (Admittedly, I did learn to run traditional SEMs as an undergrad at MIT, but such prior training is really not needed with this tool.) FEI did a great job of developing a very easy to use GUI with touch-screen control for focus, magnification to 20,000x, contrast, etc.

Beyond picking up where optical microscopes are losing resolution power, the Phenom’s potential market will also include organizations that need SEM technology but cannot afford the typical >$200,000 investment for a traditional SEM system, plus the costs of additional personnel and facilities. At approximately one-third the price of a traditional SEM, this new tool should find broad acceptance in academia as well as industry. The Phenom is now available for purchase in Europe and North America, and sales to the rest of the world will be rolled out in 2008.

Finally, I've found the perfect tool to inspect my Shure VST-III stylus tip for wear. If only I could find someone who still knew what the stylus for a vinyl turntable was supposed to look like…

—E.K.

Labels: inspection, metrology, research, SEM

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070817: FEI Phenom - SEM for the people

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Ed’s Threads 070803
Musings by Ed Korczynski on August 03, 2007

Intermolecular blazes new trails for labs and fabs
Intermolecular, which officially decloaked at this year's SEMICON West, has taken high-productivity combinatorial (HPC) technology from a Symyx license and added test-chips/parametric-testers and informatics software to revolutionize the way new materials technology is developed in labs and deployed in high-volume fabs. Intermolecular works to provide faster time-to-market, at lower cost, and lower technology risk. Symyx’s license to Intermolecular includes the IC space, FPDs, bio-chips, MEMS, and any combination of active and passive circuit elements on a planar substrate.

Subtle differences between R&D; and process chambers mean that subtle materials properties can change final device results. Thus, while basic materials research can be safely done on R&D; tools, unit process development and subsequent process integration have to occur with high-volume manufacturing tools. These production systems are typically not flexible, and changing materials and parameters can be so slow that an experiment can take from an hour to a day to run.

“The majority of the $20+ billion in annual technology development for the industry is spent in process integration,” said Intermolecular founder and CEO David Lazovsky, in an on-site interview with WaferNEWS. Thus, Intermolecular’s ~700 applied-for patents deal with the three basic technology development stages of the industry:

-- Materials research, performing 500 experiments/wafer of basic materials properties;
-- Unit process development, reproducing 100s of processes/wafer on customer production wafers; and
-- Process integration, doing 10s of experiments/day that output parametric/wafer-level reliability (WLR) data.

The company has invested substantial resources to increase staff up to ~70 people with backgrounds in process, equipment, test-chip design, software, and surface chemistry. Investment in lab space and hardware has led to unique tools to process full wafers and also rectangular silicon “coupons,” parametric testers, and an Applied Materials’ Endura PVD tool that allows for correlation experiments between combinatorial modeling and high-volume production tool performance.

“Gradients are terrific if you’re just looking for materials properties. But at the device level for the IC industry, having a gradient across the device won’t be of any use,” explained Lazovsky. "What we enable is discretized processing so you have control over an area like you would in a high-volume processing system."

Using high-volume production tools for development has always been a bottleneck, but with the plethora of new materials interactions to be tested for 32nm node IC manufacturing, there’s a tipping point. What's needed is far more than a mere doubling or trebling of efficiency -- we need orders of magnitude faster results.

Intermolecular's Tempus F-20 tool performs fluids experiments using arrays of beakers/pipettes and silicon coupons for early and middle stage screening experiments with hundreds of splits simultaneously. The Tempus F-30 (used for latter stages of screening) performs fluids experiments on full 300mm wafers, using an array of tiny (~1-in. dia) circular chambers with Teflon seals to provide 28 different experimental splits across a wafer (see figure below).


For example, with parallelism a full wafer can be processed through the following four sequential wet steps in just four minutes using a parallel processing station and an adjacent blanket processing station:
-- Pre-clean,
-- Self-assembled monolayer dep.,
-- E-less cobalt dep., and
-- Post-clean.

For integration work, a customer (or a customer’s customer) provides patterned wafers pulled from a fab line. After combinatorial depositions, parametric testers can extract device data from each of the 28 discrete splits.

The self-assembled monolayer is a molecular masking layer (MML), a novel molecule synthesized specifically to bond to various low-k dielectric films, and provide a uniform top surface for an electroless deposition. The MML was synthesized after 7635 experiments with 60 molecules ran on 25 wafers in 5 weeks…and at the end of electrical tests they found two molecules that had some of the right properties. One of these was the basis for synthesizing a new precursor for a materials supplier customer that is a low viscosity liquid at room temperature.

As another example, Intermolecular helped a leading Taiwanese foundry develop a wider process window for interconnect cleans for the transition from the 65nm to the 45nm nodes.

Fluids-based processing hardware is available for sale and license along with support. PVD tools are internally developed for collaborative development programs, and will be productized for sale as hardware like the fluids tool. ALD is on the company's roadmap.

Since Intermolecular focuses on integration, investments in test-chip design software and parametric test hardware allow for sophisticated optimizations of circuit functions. Working with partially processed wafers, Intermolecular rapidly screened >12,000 sets of flash memory cells using PVD, followed by additional screening to optimize the read/write pulses to match the properties of the new cell. “So there are combinatorial methods used to develop the materials system, and there’re also combinatorial methods used in how you operate the cell. That’s part of the solutions space, and it’s non-trivial,” commented EVP of business development Gustavo Pinto.

Intermolecular seems to have found a truly new and powerful methodology to integrate new materials into advanced ICs. With the ability to do deposition experiments on at least 28 discrete areas of a wafer and then test and extract productive information from massive data dumps, you can get a lot of work done. Rarely is the use of clichés like “paradigm shift” or “revolutionary” justified…but this might well be one of those rare cases.

—E.K.

Labels: combinatorial, development, HPC, materials research

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070803: Intermolecular blazes new trails for labs and fabs

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