Ed’s Threads 080613
The last musings in this blog on Friday the 13th of June, 2008

Process integration drives the IC industry
The next 10 years will witness more changes in mainstream manufacturing technology for ICs than in the last 40 years combined. An industry based on “what have you done for me lately” can never rest on its laurels, and so innovation must continue, despite limits in 2D scaling. With rapidly escalating costs projected for 32nm node and smaller digital CMOS manufacturing, it is inevitable that IC companies look to analog, packaging, and heterogeneous integration to add relatively greater value for lower cost and risk. Unique process integration challenges at each fab will drive everything for the next ten years, as shown recently by presentations at the recent International Interconnect Technology Conference IITC., some of which I've already discussed in this blog.

What are the ramifications of all of these subtle changes? With basic “unit-process” building blocks fairly well established, it is likely that the only fundamentally new tools to be developed will be for metrology. The current generation of thin-film, lithography, and thermal processing tools are extremely productive and should continue to be used with modest evolutionary upgrades over the next 10 years. The only exception to this is probably EUV lithography, which is still under development but shows promise.

New integration of old processes can be seen in the evolution of barrier layers for Cu metal in dual-damascene structures. At IITC, Novellus showed that PVD Ti/TiN is the newest Cu barrier to replace Ta -- though Ti is the standard barrier for Al metal lines it was replaced by Ta when the industry first began using Cu lines. Though less expensive than Ta, Ti can react with both fluorine (in FSG dielectric) and Cu and so was not considered to be an acceptable barrier. However, now that FSG has been replaced with SiOC in many fabs, a 5nm thin TiN layer (formed with 50 at% N) capping on Ti stops Cu diffusion. An ultra-thin PVD Ti wetting layer on top of the TiN provides a good surface for ECD fill of Cu.

NEC has targeted high-reliability automobile MCUs, and examined PVD Ti/Ru barrier metal for these applications. After 7 hours at 350°C, Ti diffuses into the Ru, but no Cu diffuses through the Ti. PVD-Ru with (001) orientation can be removed by CMP using conventional slurry for Ta/TaN removal. The Ru barrier achieved 12% lower resistance than the conventional Ta type barrier for 70nm wide Cu lines, while time-dependent dielectric breakdown (TDDB) was unchanged. The Ru/Ti barrier shows 35× longer lifetime (T50) than Ta/TaN. Whatever process is finally developed will run for over 10 years with essentially no changes, as per the supply contracts to the auto industry. I toured NEC Roseville recently and saw old 200mm tools being installed with plans to run for >10 years using ≥150nm node processes.

Low-k air-gaps are also great examples of using old unit-processes in new ways, since CVD oxides (SiOx and SiOC) and spin-on polymers already well developed will be used, while established lithography and etching technologies will complete the integration. EDN's Ron Wilson covered many of the latest air-gap integration details from IITC in his fine blog, but the most important consideration is that no new manufacturing tools are needed to make them happen. Designs may need to be tweaked, and the process integration will be challenging, but this approach is relatively low-risk and may be integrated into older fab lines.

Further proving that “there is no more noise (…there is only signal),” IMEC’s Michele Stucchi at IITC examined the effects of inherent line-edge roughness (LER) and via misalignments on the Efield and electrical breakdown between wires. An enhanced electrical field between adjacent lines is induced by LER-induced reduction in spacing. Compared to a nominal electrical field between lines with zero LER, a probabilistic analysis results in enhancement to the field, which can be a factor >2 in 30nm spaced lines. For wires with 30nm spacing, Efield may be high enough to guarantee at least one bridge in 20μm of line length. For via misalignment of 10nm in standard dual-damascene structures with 30nm spacing, the field enhancement can be a factor >3.

An amazing example of tricky process integration to eliminate variability in lithography was shown by Matthew Breitwisch of IBM, in describing work with Macronyx on phase-change memory (PCM) technology. Ge2Sb2Te5 (GST) was the first material investigated which changes from a high-resistance amorphous structure to a low-resistance crystal at ~170°C. A PCM cell is made up of a variable resistor in series with an access device (which may be a diode, BJT, or FET), and current flux near one million A/cm2 is needed for a few nanoseconds to create the change. To concentrate the current in programming, uniform small pores are achieved using a key-hole (a.k.a., “pinch-off CVD”) process:

- blanket oxide, hardmask and nitride depositions,
- lithography,
- anisotropic etching through the dielectric stack,
- an isotropic oxide etch to create an undercut below the hardmask, and
- conformal polysilicon CVD to form consistent 43nm wide keyholes.

The keyhole widths are controlled by the oxide etch and the poly CVD, and not by the lithography, such that equally sized pores form in the middle of line spaces of varying width…all without any new unit-processes.

With razor-thin process windows and systematic process-design interactions, each fab may have to optimize its own integrated process flow. If each fab runs a unique flow, then a mask-set run on one line will yield very differently on a second line, and this reality may create problems for companies trying dual-sourcing with foundries.

New materials and evolutionary upgrades to old materials will continue to support new integration schemes in fabs, while most of the tools will remain the same. However, OEM applications labs will run non-stop as fabs try new designs-of-experiments (DOE) for new integration schemes. It will be increasingly difficult to get process information out of fabs, since each line will have to be set up with unique tricks and integration schemes. Designers will have to really start innovating, as digital CMOS shrinks no longer guarantee lower cost and higher performance.

There will be many IC types that will probably never be designed at the 32nm node. A friend working on a graphics processing chip explained to me that they needed to go to 65nm to get a speed improvement for their target application, but their modeling shows that additional speed will now provide no user benefit. Going to 45nm adds huge design costs and manufacturing yield risk, and so they now plan to stick to 65nm but work on cost and power optimization in re-design. Their next 65nm chip may use 3D interconnects or integrated passives for improved performance, however, so innovation will continue… just in new directions. Such is the blessing/curse of “living in interesting times.”

Henceforth, my challenges will be elsewhere. This is my last blog post on my last day as a Technical Editor for Solid State Technology magazine; I am resigning to pursue other interests, first of which will be an immediate 8-week sabbatical. When I return, I will probably work for the semiconductor manufacturing industry, in an as-yet undetermined capacity that doubtlessly will be "interesting." I thank PennWell Publishing for years of rewarding employment, and wish the company well. Special thanks to James Montgomery, who diligently and masterfully copy edited most of these 76 postings.

—E.K.

Labels: 32nm, 3D, airgap, CMOS, copper, IITC, integration, interconnect, process, research

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080613: Process integration drives the IC industry

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Ed’s Threads 20080331
Musings by Ed Korczynski on March 31, 2008

MRS meeting covers nanostuff and microthings
Over 4000 researchers were in San Francisco last week for the annual Materials Research Society (MRS) spring meeting, to discuss advances in materials for electronics, energy, health, and transportation. Over 40 technical session run in parallel, with >10 sessions of interest to the semiconductor manufacturing industry at any given time. Theory and results for new IC memory cells, extensions of CMOS logic, and future quantum-dots and nano-rods were shown. Graphene still seems like a possible replacement for silicon in ICs.

In his Kavli plenary lecture in nanoscience, Prof. A. Paul Alivisatos of UC-Berkeley described recent work by his group and others on transformations in nanocrystals. Chemical transformations can be used to obtain complex nanocrystalline structures though sequential chemical operations. In an example, CdSe reacted with Ag+ to form Ag2Se which could then be combined with Cd2+ to completely reverse back to CdSe, while the volume of the nanoparticle was completely preserved. Such cation exchanges can occur in semiconductor nanorods and hollow spheres with shape preservation, but when shapes do transform their final forms are currently difficult to predict.

Much of the new materials work is targeted toward finding nanoscale structures which can switch between two measurable states to function as memory cells. Two of the newer random-access memory (RAM) cell types under development are phase-change RAM (PRAM) and resistive RAM (ReRAM). With Numonyx now officially launched to commercialize PRAM along with Flash, there were many papers looking at manufacturing process flows to optimize the deposition and programming of the antimony-telluride (SbTe) family of “calcogenide” materials which undergo thermally-assisted transitions between crystalline and amorphous phases. Independent of the MRS meeting, materials supplier ATMI recently announced co-development plans with Ovonyx for calcogenide CVD precursors.

ReRAM using metal-oxides as switching elements comes in two fundamentally different variations: one-time programmable through the growth of nano-metallic-filaments, and reversible through ionic transport between electrodes. ReRAM materials may be used in PRAM-like cells, or also used as the switching element in cross-bar architecture arrays. HP Labs, US NIST, and Hokkaido University all showed advances in hybrid circuits built using cross-bar arrays.

For extensions of CMOS logic, with a somewhat clear path forward in new materials for high-k and metal gates, a lot of research now centers on doping technologies. G. Lansbergen et al. (B3.7) from TU Delft (The Netherlands) along with Purdue (USA), University of Melbourne (Australia), IMEC (Belgium), and Caltech (USA) showed the ability to work with a single Arsenic dopant atom in a p-MOS finFET; their experiments represent the first evidence of the ability to engineer the quantum state of a single-donor electron by surface gate control. While single-ion doping is way beyond today’s fab specs, more precise control is needed for the placement of often <100 atoms for channels and contacts.

Wilfried Vandervorst of IMEC showed that Laser Spike Anneal (LSA) which is essentially “diffusion-less” calls for re-integration from prior rapid-thermal annealing (RTA) schemes where lateral diffusion is significant. Due to the very low thermal budgets needed to form ultra-shallow junctions (USJ), LSA is more subject to pocket dopant fluctuations than spike anneals. Random dopant fluctuations must be controlled, along with structural variations on gate cross-sections which appear as undercuts and footing. LSA helps equivalent oxide thickness (EOT) scaling for gate dielectrics by elimination of a 2-3Å thick re-growth layer. However, to ensure reliability in gate stacks, an RTA step can be added after LSA to improve the situation somewhat. Looking forward to embedded SiGe, LSA so far induces junction leakage and defects gliding along certain crystalline planes which unfortunately relaxes desired strain. LSA for embedded SiC, however, avoids SiC relaxation which improves the strain retention in nMOS. Gate profile control is critical for diffusion-less USJ, which may mean gate-last integation schemes will be easier to integrate.

Karuppanan Sheker, of SemEquip, presented on how to use cluster-carbon implants to improve the Si:C layer formation. There is ~2% limit to how much C can be substituted in silicon lattice. At the VLSI Technology Symposium 2007, IBM showed [C]sub of 1.65% with mono-atomic C implants and pre-amorphizing implants (PAI). Using clustered carbon eliminates the need for the PAI and provides [C]sub >2%. The source is two benzene rings in the form of C14H14, which upon striking a silicon crystal in the 6-10keV implant energy range automatically induces amorphization with depth of 20nm-40nm. The greater the amorphous layer thickness the higher the percentage C which can be substitutionally incorporated.

Newer finFET architectures, which may first be used for SRAM arrays, require unique integration flows. Mark van Dal, NXP-TSMC Research Center, showed that when implants into fins amorphized the silicon material, the re-crystallization in complex fin shapes results in scattering and other sources of variability. The exact reason for the device degradation is not known, but using either BF2 or B+Ge implants (both of which induce amorphization) result in more transistor variability. At fin widths of 1µm there is no difference, but for fins <0.1µm wide the effect is clearly seen. When non-amorphizing B implants are used, no device performance degradation is observed.

— E.K.

Labels: CMOS, finFET, graphene, materials research, nano, PRAM, ReRAM

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080331: MRS meeting covers nanostuff and microthings

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Ed’s Threads 080211
Musings by Ed Korczynski on February 11, 2008

IITC process units and integration
The International Interconnect Technology Conference (IITC) has issued its 11th call for papers, and for a change it will explicitly focus on unit processes (and new materials) while continuing to cover the leading edge of integration. The main deadline for paper submissions has now passed, but a limited number of late papers will be accepted until April 11th. The shift in emphasis toward covering unit processes is due to the divergence of integration options moving forward.

Manufacturing ICs on silicon wafers is very complex; hundreds of “unit process” steps (e.g., clean, inspection, etch, deposition, etc) are combined into dozens of “integrated process modules” to form functional structures. One integrated process module may form high-performance transistors, another module forms contacts to transistors, and yet another module forms interconnects between contacts. Many of the unit process steps are copied between modules, and thus has it been since the 1960s.

During the last twenty years, the digital CMOS shrink has been the one process integration direction uniting all the different unit processes under development. The set of requirements for the next node/generation of digital CMOS was always the most challenging for equipment manufacturers working on unit processes. However, starting with the 45nm node, the integration of unit processes has become so complex that there is no one obvious solution for all fabs.

Dr. Thomas Caulfield, EVP of sales, marketing, and customer service for Novellus Systems and former technology executive with IBM, talked with WaferNEWS about the changes in the development of unit-processes in the industry. “As an industry becomes commoditized, how to you differentiate? You either have more efficient design, or more efficient unit processes that allow you to get more productivity or functionality out of the manufacturing. So the last thing you want is the same integrated process,” explained Caulfield. With the leading-edge of IC manufacturing ever increasing in complexity, the productivity of tools used in the fab must increase just to keep costs the same.

Consider the process module to form contacts as an example of integration. Today, the formation of advanced contacts requires something like the following sequence of unit processes:

1) CVD of a blanket dielectric layer,
2) Thermal treatment to stabilize/planarize,
3) Metrology to inspect the layer,
4) Photoresist mask spin-on and bake,
5) Lithography to form initial openings,
6) Treatment to shrink the opening,
7) Metrology to inspect the photoresist,
8) Etch of the dielectric through the mask,
9) Strip/Ash the remaining photoresist,
10) Clean/Treat the dielectric openings,
11) Metrology to inspect openings,
12) Deposit metal barrier layer,
13) Deposit metal for contact,
14) CMP of metal layers, and
15) Metrology to inspect contacts.

Each of these steps has sub-steps too.

In the past, major developments could be described and documented at the integrated process module level, allowing much of the unit process details to be IP secrets. The amazing innovation that enabled digital CMOS shrinks is now pushing against limits of atoms and wavelengths of light, and it now seems clear that further pushes will be ever more expensive. Fabs will also work to integrate analog, RF circuitry, integrated passives, and 3D packages using essentially the same unit processes. “It’s no longer Moore’s Law one-size-fits-all with all the focus on the next generation technology,” explained Caulfield.

Since the integrated process details are now quite sensitive, technologists are relatively more able to talk about developments in unit processes. From an equipment supplier perspective, of course, unit process development does not occur in isolation. “You develop a process capability because you have an application and market in mind,” explains Caulfield. “It’s not that we don’t keep doing that, but today we find customers using the same unit processes in novel ways.”

EDN’s Ron Wilson recently blogged about the IITC call-for-papers and the ramifications of unit process development for IC designers. He considers that porting a physical design from one fab to another may soon require significant inputs from equipment manufacturers, but it is highly unlikely that designers will ever have to talk to OEMs about GDSII files. Using the example of the contact module, the variations in the geometry of the metal contact plug are due to the interdependencies between the different unit processes. Sometimes the source of a structural variation can be easily identified as one unit process, but more often it is impossible to separate out which of the unit processes were to blame. If the diameter of the contact is too large, was the resist overexposed, or was the dielectric overetched?

In addition to the complexity that can be seen in final device structures on the atomic-scale, there are many sacrificial thin-film layers and other “hidden” unit processes within the integrated flow. “It’s funny to watch people debate how something was done based on the data from reverse engineering a final chip,” commented Caulfield. “There’s just no way to conclusively determine the process sequence afterwards with so many sacrificial steps in the integration scheme.”

For example, Novellus sells a pseudo-ALD dielectric tool that forms what they call a pulsed-deposition layer (PDL). Some DRAM fabs use a sacrificial dielectric which they remove with a wet etch, and for this integration scheme the PDL provides no advantage. However, other DRAM fabs use CMP to remove the equivalent sacrificial dielectric, and for them the PDL provides an advantage. The reasons for choosing one integration approach over another are very complex. “People are leveraging unit processes in different ways to try to get the best results while going to higher density,” explained Caulfield. “Productivity or manufacturability differentiation through proprietary integration schemes is the goal—and there are many ways to skin the cat—that provides competitive advantage.”

OEMs have always sold tools that perform basic unit processes, and fabs have always fine-tuned unit processes for integration into modules. The only fundamental change now is that fabs must manage extreme complexity at the same time that most chips have become commodities. “It’s a big problem that the industry is adding manufacturing complexity at the same time that chips are becoming commoditized,” expressed Caulfield. “If you’re not on a curve to take cost out of running a manufacturing tool, then you’ll become the problem that gets worked out of the equation next.”

—E.K.

Labels: CMOS, IITC, integration, OEM, PDL, process, unit

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080211: IITC process units and integration

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Ed’s Threads 080101
Musings by Ed Korczynski on January 01, 2008

2007 odds and ends
High-k (HK) and metal-gates (MG) for CMOS transistors are real and here now, with Intel deciding on HK-first but MG-last for process integration. What is the temperature limit for MG processing such that the HK remains amorphous in this flow, and how many other elements are alloyed with hafnium and oxygen in the final film? IBM and SEMATECH and most of the rest of the world seem to be working on HKMG-first integration.

IBM in the US has sold 45nm bulk silicon manufacturing technology to SMIC in the P.R. China. I remember being in Shanghai in 1995 when people in China talked about getting 250nm (then “quarter micron”) technology from US companies, and it was then deemed too powerful to let go; now such technology sells for pennies on the ever depreciating dollar. Meanwhile, Intel is reportedly still on schedule to open a 90nm logic fab in China.

Indian semiconductor fab plans seem to lack the political will needed to become real. An anonymous comment left on my prior blog entry about India's plans for its "Fab City" stated, “so far nothing happened. no electrical infrastructure and no water pipes. government is only fooling to promote the nearby real estate ventures.” Informal discussions with Indian expatiates at IEDM last month seem to confirm this perspective. The official Web site for the government now lists "Nano-Tech Silicon India Ltd." (NTSI) as a solar fab to be built -- just seven months ago the government insisted that it would soon be a 20K wafer starts/month IC fab. Despite delays in infrastructure, companies seem willing to try to start-up photovoltaic fab lines in India along with the rest of the world (scroll halfway down the page to see the list of promised PV projects).

With the price of oil nearly at US $100/barrel (less in other currencies), most of the world has decided that solar energy might be worth investing in for a while. Applied Materials continued to acquire its way into OEM dominance, while Oerlikon did a spin-out and acquired a top executive. (I recently talked shop with top PV execs at both AMAT and Oerlikon about their respective strategies.)

Meanwhile, subsystems suppliers like Advanced Energy and Edwards have shifted resources to follow the PV money. Nanosolar printed its first CIGS thin-film PV cells at its new line in San Jose, CA. HelioVolt announced its first fab to produce printed CIGS cells. Dick Swanson of SunPower gave a great presentation at IEDM (Session 14.1) on development of silicon solar cells, showing that manufacturing efficiency increases should cut final installed PV system costs 50% by 2012.

Never trust a semiconductor process engineer who isn't a great cook. It's all about recipes either way, and I've come to the unreasonable conclusion that all good process people like to play in the kitchen too. Baking holiday cookies reminds me of systematic yield losses and design-for-manufacturing (DFM) pattern-centric solutions -- in both cases you need uniform distribution of features across the surface to ensure uniformity. The more narrow the process window, the more you have to control repeatability across the cookie sheet (or silicon wafer).

From the wonderful people at the Annals of Improbable Research we get the yearly Ig Nobel Awards . My personal favorite award for 2007 -- due to love of Toscanini's Ice Cream -- is the award in chemistry given to Mayu Yamamoto of Japan's International Medical Center, for developing a way to extract vanillin from cow dung (REFERENCE: "Novel Production Method for Plant Polyphenol from Livestock Excrement Using Subcritical Water Reaction," Mayu Yamamoto, International Medical Center of Japan.) Moreover, kudos to Toscanini’s for creating a new ice cream flavor and introducing it at the Ig Nobel ceremony, called "Yum-a-Moto Vanilla Twist."

Speaking of twists, 2007 was also another year of consolidation across various equipment/process segments (Lam/SEZ, KLA-Tencor/Therma-Wave/FabSolve, Aixtron/Nanoinstruments, MKS/Yield Dynamics, and TEL/Epion to name just a few). Notable deals happened in the intersection of litho and design (Cadence/Invarium, Blaze/Aprio, and in late 2006 ASML/Brion), as well as test (Teradyne/Nextest, Verigy/Inovys, Rudolph/Applied Precision). Also, private equity had a major presence in the industry, particularly early in the year, in deals for Edwards' vacuum/equipment biz, backend firms STATS ChipPAC, UTAC, and UK dep/etch firm STS. And even AMD looked overseas for much-needed external funds.

One surprising end to 2007 was the Republic of Lakotah formally withdrawing from all treaties with the United States of America, and reclaiming sovereignty as a nation and over its traditional grounds. Maybe someone can build an IC fab there.

After Motorola's advanced fabs became Freescale and then moved R&D to France and then New York, and after Texas Instruments decided to end R&D at 45nm, and after the Silicon Valley Technology Center (Cypress’ former R&D fab) bought the Advanced Technology Development Fab, it’s time to pause for a moment of silence. SEMATECH in Texas is dead; long live SEMATECH in New York!

— E.K.

Labels: CMOS, consolidation, Fab City, HK+MG, photovoltaic, SEMATECH

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080101: 2007 odds and ends

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Ed’s Threads 071123
Musings by Ed Korczynski on November 23, 2007

Printed silicon RF-IDs by Kovio
Humans like to tag and track things. This natural tendency has led from physical tags and labels to bar-codes and today radio-frequency identity (RF-ID) chips. There has been controversy over the possibly use of “active” RF-ID tags being used to secretly track people, but simpler “passive” RF-IDs seem inherently much more difficult to secretly track since they generally require a sensor to be in very close proximity. Plus, disposable items just aren’t great at tracking people, so we can unreservedly applaud printed silicon ICs for passive RF-IDs from privately held Kovio, Inc.

Kovio, founded by a team of scientists in the MIT Media Laboratory, has come out of R&D stealth mode with a printable silicon IC technology with first applications for extremely high-volume manufacturing of passive RF-IDs. In an exclusive interview with WaferNEWS, Vikram Pavate, Kovio’s vice president of Business Development, discussed the applications of this new printed IC technology. The only manufacturing details released so far are that minimum linewidths will be around one mil using liquid-phase inorganic “inks” for all film precursors needed to form CMOS silicon thin-film transistors (TFT), and the fact that the substrates will be flexible foils. This combines the low cost of graphics printing with the power of silicon-based semiconductors that can function at frequencies of MHz and above.

Many companies and R&D labs have been aiming at getting the electron mobility—expressed in units of cm2/(V·s)—of organics semiconductors up to the 0.5-1.0 range of amorphous-silicon TFTs. In contrast, Kovio’s all-printed silicon TFTs are claimed to exhibit electron mobility of ~80 cm2/(V·s). The team at Kovio includes technology executives from Spansion along with people from the former Matrix Semiconductor—which pioneered the use of deposited active layers in commercial chips.

“We’ve been able to start with all the conventional materials set used by the semiconductor industry, and creating a new paradigm on how you manufacture circuits. You’re working with dielectrics and metals that people are used to work with,” explained Pavate. “We’re very complementary to traditional silicon; traditional silicon will always address high-end RF-ID and reader chips.”

Based on claimed breakthroughs in nanotechnology and materials science, Kovio has developed functional electronic inks include silicon, doped silicon, metals, and insulators. Combining functional electronic inks with high-resolution graphics printing technologies, Kovio has printed high-performance silicon CMOS TFTs on flexible substrates at a fraction of the cost of conventional lithography-based silicon technology. The significantly lower cost is possible as a result of additive digital printing processes, lower capital expenditures, and faster cycle time.

Kovio’s high mobility CMOS allows for work with synchronous protocols, where the signal-to-noise ratios are better. “With these results we can print CMOS, while most organic electronics have been only PMOS,” said Pravate. “We are the first company to report a printed PMOS/NMOS device.” Kovio's technology is also attractive from an environmental and energy consumption standpoint. “We use 0.05% of the hazardous gases and 25% of the power that a traditional silicon fab would use. Plus, you can print these in a day or two, so there’s a significant cycle-time advantage we get as well,” asserted Pavate.

To accelerate the commercialization of its technology, Kovio has announced two separate joint development and supply agreements with Toppan Forms Co. Ltd., a world leader in printing businesses, printable electronics and digital information technologies, and Cubic Transportation Systems, Inc., a subsidiary of Cubic Corporation, the world's leading turnkey solution provider of automated fare collection systems for public transport.

“Our initial focus is to provide the market with low-cost RF-ID. Then we’ll add sensors and displays working with partners to create what we call item-level intelligence. One example could be a glucose-sensor on a medicine bottle that would inform specific dosing.

The market for passive RF-ID chips for access-cards, library collections, and high-end transit cards is projected to be $2.5B this year. “We are using graphics printing tools, and today most of the industry is using an older generation chip technology to make RF-ID. They use 0.18 or 0.13 micron node processing on fully-depreciated fabs, and their chips still cost 10-15 cents,” asserted Pavate. “How can they meet demand without building new fabs with tool depreciation adding additional cost?”

Pavate says that general consensus is a 5 cent inflection point could really stimulate demand, but even that cost is too high for a lot of mainstream retail or for a shipper like the US Post Office or FedEx. The US Post Office moves ~260 billion units a year, and can only consider RF-ID tags that are very low cost. “For the type of devices we’re talking about, 20-30 micron linewidths is adequate,” explained Pavate, so printed processes should be more than adequate and allow for additional cost-reductions. “You focus on improving the printing speed, or the web-width.”

Retail and pharmaceutical industries turn inventory several times per year, so they require very short delivery times. Kovio will print chips and/or antennas and then ship those to customers who produce final system for end-users. “These are printing fabs, and the first thing you do with printing is you think about co-locating it,” explained Pavate. “I see a path where large apparel or automotive or pharmaceutical manufacturers would have the RF-ID line next to the current factory.” Kovio will start discussing roadmaps in general by 2Q08, with pilot production planned for 2H08. Stay tuned…the world of silicon IC production just got a lot more interesting.

—E.K.

Labels: CMOS, Kovio, passive, printed, RF-ID, RFID, TFT

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071123: Printed silicon RF-IDs by Kovio

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Ed’s Threads 070615
Musings by Ed Korczynski on June 15, 2007

IBM HK+MG gate-first processing
At the VLSI Symposium on June 14th, and after months of a mainstream press hype-war with Intel, IBM finally unveiled some of the details of its new high-k/metal-gate (HK+MG) transistor technology. Mukesh Khare, IBM project manager for high-k/metal-gate development, presented integration details of the new transistors while keeping specifics of materials and processing confidential. The key information is that their HK+MG “gate first” approach keeps the same processing sequence used by traditional SiON gates, allowing for both technologies to be run on the same line and minimizing integration costs.

“We did a lot of work to look at gate-first and gate-last, and both approaches have challenges,” explained Khare, in an exclusive interview with SST and WaferNEWS. “We picked the approach that is simple, scalable, and also migrate-able.”

Gate-first is simple in terms of changes to existing processes, and looks scalable to smaller device geometries. “Migrate-able” means making it easy to port designs from SiON transistors. Indeed, gate-first processing seems to be the best overall approach -- if you can find a material that can withstand the high temperatures used in device annealing. Keeping most of the existing process flow intact, 45nm will still use tungsten plugs for contacts.

Transistor formation typically requires ~1000°C annealing to allow atoms to settle into proper places after ion-implantation, which inherently damages silicon crystals. Any gate materials in place during annealing must withstand such temperatures without losing their properties. In particular, the high-k dielectric material must maintain a certain composition and material phase to ensure that the transistors do not leak current.

All IBM will officially say to date is that its gate-first high-k material is hafnium-based, which is the currently known default standard, but they will not yet specify anything else. The material is likely to be a blend of hafnium, silicon, oxygen, and nitrogen, which can be seen as just adding the hafnium to the SiON currently used. Hafnium atoms have a relatively higher oxygen coordination number and are simply larger (atomic number 72, compared to silicon at number 14, and oxygen and nitrogen at 8 and 7, respectively), so adding them to the SiON currently used increases the dielectric constant of the layer based on density functional theory. The thickness of the inversion layer under the gate (Tinv) with conventional oxynitride is typically, at best, 18-19 Å -- IBM’s HK+MG transistors reportedly demonstrate Tinv ~12Å, something achieved, by working for over 10 years on fundamental materials engineering.

Though not needing any fundamentally new metrology techniques, every film will require control. For example, compositional changes with nitrogen depth have already been used with nitrided-oxide gates (SiO:N), so one possibility is a nitrided-hafnium silicate (HfSiO:N). Nearly all the recent HK dielectrics that have been shown for CMOS transistors have been stacks of layers with atomic-level engineering of the interfaces. The specific composition and gradients within the layers are officially secret, but it is highly likely that there is at least one atomic layer of SiO at the bottom.

HK+MG transistors at nanometer-scale nodes are constrained by the same trade-offs between speed and leakage (for HP or LSTP circuits, respectively) as with SiON+poly transistors. Engineering the dielectric stack to be either fastest/leaky or fast/tight for a target HP or LSTP, there’s a single HK gradient-stack and one metal used for both NFET and PFET gates. Poly-silicon tops the metal gates. “After more than three years on the 300mm pilot line, there’s been a lot of learning and we’re on track,” Khare noted.

For planar devices, there are more options in terms of ALD, CVD, or PVD, explained Khare. He claims that the cost to use HK+MG is similar to that needed for any new technique like using a dual-stress liner, and so it adds minimal additional cost to the final wafer, but not all designs will need the performance improvement so some chips at 45nm and 32nm will still use SiON+poly. “It depends on the product needs. It is a very powerful technology. It’s very simple,” stated Khare. “The materials challenge was very high k, and that’s one thing we focused on.”

—E.K.

Labels: CMOS, high-k, HK+MG, IBM, metal gate, transistor, VLSI

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070615: IBM HK+MG gate-first processing

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Ed’s Threads 070427
Musings by Ed Korczynski on April 27, 2007

Planning for life after CMOS commoditization...today
It’s hard to feel upbeat about the future of mainstream semiconductor manufacturing after attending this year’s SEMI Strategic Business Conference in Napa, CA, where presentations detailed the end of the good times. After decades of leading the world in high-tech value-adding, the IC business is now mature and just another part of the global electronics industry. This is nice enough, unless you remember the record revenues, profits, and capital equipment expenditure levels of the 1990s.

Trends within the IC industry indicate that the average cost to develop a new IC product has risen from $10M at the 90nm node to $50M at 65nm. With a targeted 10x return on research and devleopment over the life of the product, you need to see over $500M in chip sales for a single 65nm product. Remembering that consumer chips typically sell for $5 each in quantity, that means before even starting a new 65nm chip design you need to show demand for 100M units, which will effectively lock out a number of applications spaces, noted Wil Josquin, VP of strategy and innovation for NXP Semiconductors.

In his concluding keynote presentation, Art Zafiropoulo, CEO of Ultratech, included a slide from Freescale showing the percent of investment into a final IC product going toward packaging has gone from <20%>50% in the last five years. His final slide ended with the final line reading that advanced packaging will be the only differentiating technology. Amkor’s David Hays, VP of business development, wafer level processing, reminded the audience that, “There’s no way to get all the features and functions in cell phones that we all want using old chips and old packages.” For example, Motorola’s trend-setting V3 RaZR handset includes six chip-scale packages (CSP) plus 14 wafer-level packages (WLP).

Despite providing substantial value, outsourced semiconductor assembly and test (OSAT) providers such as Amkor or STATS/ChipPac find it difficult to make a profit. “The industry doesn’t want to pay us to do the work we do,” Hays lamented. “It’s like Walmart -- they’ll say what they’re willing to pay for it, and it’s up to you to figure out a way to make a profit.” There are seemingly no more obvious and easy solutions available. If you do a silicon chip shrink from 90nm to 65nm nodes for cost savings, you may find that the added packaging cost to handle a smaller chip with tighter pitches negates any saving in the silicon.

Consumerization drives rapid electronic product life cycles that stress the supply chain. Scott DeBoer, Micron’s director of process development, reminds us that commodity pricing can be very volatile —e.g., NAND flash spot prices averaged $9.50 on Dec. 1, but had sunk to $5.15 by Jan. 26. Extremely tight coordination is required between EDA, IP, fab, packaging, and ATE partners to have any hope of first silicon right. Plus, after decades of evolution, nanometer-scale CMOS logic technology has reached commoditization, such that the chip itself just doesn’t make the product any longer. Future added-value will come from software and advanced packages and bundled-internet-subscriber-services, not from the ICs which power it all.

With Intel sending 90nm logic technology to China, and TI stopping CMOS development at 45nm, the writing is clearly on the wall. Mike Thompson, manufacturing operations GM for STMicroelectronics, did the math for why TI said no more, concluding that process technology spending as a % of development is being squeezed out by increasing efforts in software development for new products in the ASIC/ASSP world. With ~$400M required to develop a new silicon process technology, if this is 20% of the total research and development budget which is capped at 20% of total sales, then only IDMs with >$10B IC revenue can maintain independence in silicon process technology development. For logic technology, the world is settling down to just three or four independent sources of mainstream CMOS technology development: Intel, the IBM ecosystem, the foundries, and Japan.

IBM continues to lead the industry in technology innovation as the center of the collection of partners in the Common Platform Alliance (CPA). This alliance includes many design and packaging members who add value beyond the limits of silicon, such as Amkor, ARM, Analog Bits, Blaze, Chipidea, Clear Shape, Cadence, Magma, Mentor Graphics, Ponte, Synopsys, and Virage Logic. The industry continues to innovate using current business models, though we should expect to see many shake ups below the first-tier of IDMs, OEMs, and OSATs.

Major IDMs will continue to manufacture in-house, though they will both provide and use more and more foundry services. Fabless companies will continue to function as they have in recent years, with clear distinctions between the top-tier and all others. Medium-size IDMs will partner to remain “fast-followers.” If you’re supplying equipment or materials to leading-edge fabs, expect that greater purchasing power will consolidate into fewer hands. Overall what can we expect from the new reality of CMOS logic commoditization? Keep up the good work, and you might even get paid some day.

— E.K.

Labels: business, CMOS, commodity, fab, IC, strategy

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070427: Life after CMOS commoditization

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