Ed’s Threads 071211
Musings by Ed Korczynski on December 11, 2007

It’s time for IEDM, and ~1600 leaders of the CMOS fab world have gathered in Washington D.C. to announce the latest, greatest in new devices. The first big news concerns high-k/metal-gate (HK+MG) transistors for 45nm node and beyond processing. With many parallel sessions covering the most important technology trends in IC manufacturing, it is impossible to mention all of the great results presented by teams from around the world (apologies to: ST/NXP/Freescale, Fujitusu, MIRAI, NEC, SELETE, Sony, Toshiba, and TSMC).

Presenting on behalf of 53 co-authors, Intel VP Kaizad Mistry disclosed some real details of the company’s latest 45nm process technology featuring HK+MG. Finally answering the gate-first or gate last question with “both,” Intel has decided that the tough integration challenges for high performance logic can be best met with HK first but MG last processing. The transistors feature 1.0nm equivalent oxide thickness (EOT) dielectric, based on an atomic layer deposition (ALD) of a hafnium-based compound -- no additional details yet on other elements likely to be used in this ALD step, whether the phase of the final material is amorphous or crystalline, or what is the specific interface from the HK to the highly-strained channel. (In a side conversation after Mistry's talk, Intel Fellow Tahir Ghani confirmed the need for this interface, but would provide no details, only noting that it is critical for mobility.) pMOS performance is improved by increasing the Ge content of the embedded SiGe to 30% (from 23% @ 65nm, and 17% @ 90nm) and by reducing SiGe proximity to the channel. Lithography utilizes 193nm dry patterning, though some masks require two exposures in two resist layers along with a sacrificial hardmask. Transistors feature 35nm physical gate length, ultra-shallow junctions, and nickel silicide. Drive currents are benchmarked at 1.0V, a low 100nA/μm I_OFF and at 160nm contacted gate pitch. pMOS drive current of 1.07 mA/μm (51% improvement over 65nm), while nMOS drive current is 1.36mA/μm (12% better than 65nm). SRAM arrays with cell sizes of 0.346μm² and 0.383μm² (performance dependent) and multiple microprocessors are already in volume production, with claimed excellent yields.



Figure. TEM micrograph of 45nm Intel high-k + metal gate pMOS transistor. (Source: IEDM2007 10.2)


Intel’s gate-first/last HK+MG process flow for 45nm transistors is as follows:
- STI, well, and V_T implants,
- ALD (18-20Å) of HK gate dielectric,
- Polysilicon deposition and gate patterning,
- Source/drain extensions, spacer, Si recess and SiGe deposition,
- Source/drain anneal, Ni salicidation, ILD₀ deposition,
- Poly opening CMP, poly removal,
- pMOS work-function metal deposition,
- Metal gate patterning, nMOS work-function metal deposition, and
- Metal gate Al fill and Al CMP, etch-stop layer deposition.

IMEC and its partners (TSMC, Matsushita, Infineon, Samsung, and NXP) showed a low V_T CMOS gate-first HK+MG using TaC-based metals and laser-only annealing. Symmetric low V_T values of ±0.25V and unstrained I_DSAT of 1035/500μmA/μm (for nMOS/pMOS respectively) at I_OFF=100nA/μm and VDD=1.1V were demonstrated on a single wafer. To do so required Hf-based high-k dielectric capping layers of lanthanum oxide (La₂O₃) for nMOS and aluminum oxide (Al₂O₃) for pMOS to lower EOT from ~17 to ~15 while maintaining the same target V_T. HK-caps in combination with a laser-only activation anneal maintain band-edge equivalent work-function (EWF) and minimal EOT re-growth. La₂O₃ thickness control allows for V_T turning from 0.2 to 0.6 for nMOS. HfSiO shows lower V_T and higher mobilities compared to HfSiON. The laser-only anneal further results in improved L_G scaling of 15nm and a 2Å T_INV reduction over the spike reference. Lam etchers were used for gate patterning. IMEC has also been working on HK+MG for finFETs.

Prof. A. Toriumi et al. (U. of Tokyo, MIRAI-AIST, MIRAI-ASET) presented on “Materials Science-based device performance engineering for metal gate high-k CMOS.” EOT is based on k, which is based on the internal field and the polarizability of the material itself. HfO₂ has monoclinic phase, but adding lanthanum, silicon, yttrium, and/or titanium can change the phase to cubic or tetragonal, while the k increases to ~30. Adding La₂O₃ increases the crystallization temperature up to 800-1000°C (over the range of 20%-40% incorporation), and the amorphous phase has the best overall properties. Regardless of composition, leakage current depends only on the physical thickness, which shows that the leakage mechanism is pure direct tunneling. Thus, using higher-k films with equal EOT (down to ~0.5nm) significantly reduces the leakage. Flat-band voltage shift has been clearly shown to be determined only by the dipoles formed at the bottom interface between SiO₂ and HK, and not by the HK to MG interface. Scattering effects should be correlated to both the material itself and oxygen vacancies in the material.

Important information is being learned about nMOS/pMOS boundaries, according to H. Rusty Harris from SEMATECH, who gave an amazing presentation on a “Flexible, simplified CMOS using HK+MG on Si(110). “What we have shown is that if we add capping layers on top of the dielectric we do not see mobility degradation,” he said. Carrier mobilities depend upon crystallographic orientation, and changing from standard (100) to (110) orientation allows for mobility increase of 3X for holes, while electron mobility drop by ~1/2. Mixed orientation -- Si(100) for nMOS, and Si(11) for pMOS -- has been examined but process complexity, cost, and variability seem unattractive. Data for Si(110) planar CMOS is relatively similar to multiple orientation approach (with much lower manufacturing cost), though an pre-amorphosizing implant is used to minimize diffusion which is faster in (110) compared to (100) silicon. Even better results should be seen with finFETs, which inherently require orientation engineering. Using large 0.25μm planar transistor lengths (not short enough to fully realize the nMOS improvements), they showed that ring oscillators were nearly equivalent regardless of (110) or (100). Sub-threshold leakage is an important factor in LSTP optimization, and gate-induced drain lowering (GIDL) is the second biggest factor in off-state power. Without even optimizing the process flow for (110), using (110) lowered GIDL by an order of magnitude compared to (100).

CEA-LETI-MINATEC/Soitec use TiN metal over HfO₂ HK gate dielectric to explore the limits of HK+MG with SOI substrates. From a historical perspective, Takagi et al. (IEDM '97) showed that long-channel transport conditions effectively degrade electron mobility as dielectric thickness decreases. Gate lengths from 18nm to 10μm were fabricated, all with widths of 10μm, EOT 1.7nm, and 145nm BOX thickness. They consider ballistic carriers may primarily determine the conduction in sSOI short-channel devices, and invoke a “ballisticity rate” to partly explain the influence of surface roughness scattering. Si thickness down to 2.5nm for SOI has been used for both HP (I_On=780ΜMA/μm) and LP (I_OFF=10pA/μm) devices.

Meanwhile, IBM and its partners missed out on getting a HK+MG paper into IEDM this year, and instead issued a press release about 32nm development. Having publicly committed to gate-first processing, Freescale researchers in the alliance have published a paper in the Journal of Applied Physics on the crystalline phases formed using zirconium along with hafnium-oxide. Hafnium zirconate (HfZrO₄) alloy gate dielectric and hafnium dioxide (HfO₂) films were formed by atomic layer deposition using metal halides and heavy water as precursors.

–E.K.

Labels: ALD, future, high-k, HK+MG, IBM, Intel, metal gate, transistor

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071211: HK+MG real details shown at IEDM

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Ed’s Threads 070615
Musings by Ed Korczynski on June 15, 2007

IBM HK+MG gate-first processing
At the VLSI Symposium on June 14th, and after months of a mainstream press hype-war with Intel, IBM finally unveiled some of the details of its new high-k/metal-gate (HK+MG) transistor technology. Mukesh Khare, IBM project manager for high-k/metal-gate development, presented integration details of the new transistors while keeping specifics of materials and processing confidential. The key information is that their HK+MG “gate first” approach keeps the same processing sequence used by traditional SiON gates, allowing for both technologies to be run on the same line and minimizing integration costs.

“We did a lot of work to look at gate-first and gate-last, and both approaches have challenges,” explained Khare, in an exclusive interview with SST and WaferNEWS. “We picked the approach that is simple, scalable, and also migrate-able.”

Gate-first is simple in terms of changes to existing processes, and looks scalable to smaller device geometries. “Migrate-able” means making it easy to port designs from SiON transistors. Indeed, gate-first processing seems to be the best overall approach -- if you can find a material that can withstand the high temperatures used in device annealing. Keeping most of the existing process flow intact, 45nm will still use tungsten plugs for contacts.

Transistor formation typically requires ~1000°C annealing to allow atoms to settle into proper places after ion-implantation, which inherently damages silicon crystals. Any gate materials in place during annealing must withstand such temperatures without losing their properties. In particular, the high-k dielectric material must maintain a certain composition and material phase to ensure that the transistors do not leak current.

All IBM will officially say to date is that its gate-first high-k material is hafnium-based, which is the currently known default standard, but they will not yet specify anything else. The material is likely to be a blend of hafnium, silicon, oxygen, and nitrogen, which can be seen as just adding the hafnium to the SiON currently used. Hafnium atoms have a relatively higher oxygen coordination number and are simply larger (atomic number 72, compared to silicon at number 14, and oxygen and nitrogen at 8 and 7, respectively), so adding them to the SiON currently used increases the dielectric constant of the layer based on density functional theory. The thickness of the inversion layer under the gate (Tinv) with conventional oxynitride is typically, at best, 18-19 Å -- IBM’s HK+MG transistors reportedly demonstrate Tinv ~12Å, something achieved, by working for over 10 years on fundamental materials engineering.

Though not needing any fundamentally new metrology techniques, every film will require control. For example, compositional changes with nitrogen depth have already been used with nitrided-oxide gates (SiO:N), so one possibility is a nitrided-hafnium silicate (HfSiO:N). Nearly all the recent HK dielectrics that have been shown for CMOS transistors have been stacks of layers with atomic-level engineering of the interfaces. The specific composition and gradients within the layers are officially secret, but it is highly likely that there is at least one atomic layer of SiO at the bottom.

HK+MG transistors at nanometer-scale nodes are constrained by the same trade-offs between speed and leakage (for HP or LSTP circuits, respectively) as with SiON+poly transistors. Engineering the dielectric stack to be either fastest/leaky or fast/tight for a target HP or LSTP, there’s a single HK gradient-stack and one metal used for both NFET and PFET gates. Poly-silicon tops the metal gates. “After more than three years on the 300mm pilot line, there’s been a lot of learning and we’re on track,” Khare noted.

For planar devices, there are more options in terms of ALD, CVD, or PVD, explained Khare. He claims that the cost to use HK+MG is similar to that needed for any new technique like using a dual-stress liner, and so it adds minimal additional cost to the final wafer, but not all designs will need the performance improvement so some chips at 45nm and 32nm will still use SiON+poly. “It depends on the product needs. It is a very powerful technology. It’s very simple,” stated Khare. “The materials challenge was very high k, and that’s one thing we focused on.”

—E.K.

Labels: CMOS, high-k, HK+MG, IBM, metal gate, transistor, VLSI

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070615: IBM HK+MG gate-first processing

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Ed’s Threads 070525
Musings by Ed Korczynski on May 25, 2007

Intel-IBM fab hype-war and truths
It has been said that the first casualty of war is the truth…even more so in a hype-war. An interview appearing on a popular electronics industry Web site is the most recent battlefield in this ongoing hype-war between the world’s semiconductor manufacturing heavyweights. As tradeoffs in fab technology become more fundamental at 45nm nodes and beyond, different companies choose to deploy similar technologies in different ways. The truth is inherently complex and thus a bit complex to describe, and can die under the assault of hype.

Among fundamental choices today we find the following: double-patterned dry or single-patterned wet lithography for critical layer patterning, and use of porous or airgap low-k dielectric for on-chip multi-level interconnects. Intel has chosen double-patterned dry lithography and non-airgap low-k dielectrics. IBM has chosen single-patterned wet-lithography and airgap dielectrics.

As shown by Hoofman, et.al, in the pages of SST last year, there are many different airgap process flows, which can produce many different airgap structures. Airgaps may be complete or partial between lines, and this is one of the more fundamental parameters to consider in integrating the structures into real chips. Thus, airgap1 is not airgap2 (General Semantics suggests the use of “indexing” to remind us of the essential distinctions between members of any conceptual set).

Using “complete airgap” flows and removing all dielectric between lines to achieve the absolute minimum capacitance does indeed create the two general problems articulated by Mark Bohr in the recorded interview: an expensive critical-lithography mask to ensure proper via landings, and copper electromigration sensitivity. However, the IBM flow uses airgaps only in the middle of line spaces while leaving dielectric material on the sidewalls of copper lines.

The IBM airgap process exposes parts of some metal sidewalls during the tricky three-stage gap etch, but the subsequent dielectric CVD process re-coats the exposed sidewall areas prior to “pinching off” the tops of gaps. With adequate sidewall dielectric in place, via landing and electromigration issues can be minimized if not avoided. Intel’s Bohr certainly understands airgap integration issues far better than I do, but because he’s not in a position to comment on how his competitor’s process might work, he accurately and properly expressed Intel’s results in the interview, and the generic disadvantages of approaches not currently taken by Intel.

However, a statement summarizing the interview reads thusly: “Mark Bohr, Intel senior fellow, says his company looked at air-gap technology like IBM recently introduced, and dismissed it as costly and inefficient.” That's a misinterpretation. The truth is that Intel never panned IBM’s airgap technology—Bohr answered a specific question about IBM’s technology with a generic answer about non-IBM technology. Of course, Bohr can very reasonably say that he has no knowledge if IBM’s technology beyond what is muddied in the official press release. Since IBM’s marketing spun the technology truth to the point of grandiose hype, it provides easy opportunity for Intel to comment on the hype instead of the truth. (Incidentally, further information on the general concept of self-assembled nanotechnology for lithographic masking applications can be found in the most recent issue of Microlithography World.)

The IBM hype was that no new lithography is needed. Intel counters that a generic process flow for airgaps requires critical-lithography steps. The truth is that the IBM flow does use an additional lithography step for each airgap level, but it’s non-critical and the mask generation has been automated as a button in the EDA deck. Critical-lithography steps for 45nm node processing can be 10X more expensive than non-critical patterning steps. If the IBM airgap process required critical lithography for each level then it might add 20%-25% to the cost of each chip, but with non-critical lithography it might add only 5%-8%.

For most people in the world who lack experience in fab processes, subtle complexities get lost in translation and details are distorted or lost. The truth about nanometer-era fab processes is that they are all tough to develop with inherent integration trade-offs. With Intel and IBM now going down divergent paths, it’s truly difficult to assess a fab technology “leader” in anything but hype.

— E.K.

Labels: airgap, fab, IBM, IC, Intel, interconnect, low-k, self-assembly, ULK

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070525: Intel-IBM fab hype-war and truths

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Ed’s Threads 070504
Musings by Ed Korczynski on May 04, 2007 (updated June 12, 2007 to correct details of the IBM airgap etch process, which had erroneously referred to the third-step being RIE, when it is wet as confirmed by both D. Edelstein and S. Nitta)

IBM adds airgaps for faster chips
Airgaps have long been considered as structures to increase the speed of on-chip IC interconnects, though no one had developed manufacturing-worthy process flows. Only in the last year have companies such as Philips (now NXP) shown overviews of likely airgap manufacturing processes, though without production commitments. Now IBM has invented a new variation on airgaps that uses a self-assembling polymer mask layer as part of the process flow, and claims this can be a simple drop-in addition that adds only ~1% to chip cost for each dielectric layer gapped. Thus for an advanced multilevel interconnect, a ~5% cost adder should provide 35% faster chips or 15% less power consumption.

Circuit speeds are limited by the dielectric constant (k) of the insulating material surrounding metal lines, so the industry's Roadmap has focused on ever lower k dielectric materials. Unfortunately, materials engineering for a new dielectric material is difficult and expensive, and despite tremendous efforts and many false-starts over the years, the entire world has now settled on SiCOH by CVD as the lone dielectric material (k~3) that provides acceptable cost, yield, and reliability. So-called ultralow-k (ULK, aka “extreme low-k”) films are merely k~3 SiCOH with the addition of ~20%-40% by volume of nanopores to reach k~2.4. More nanopores cannot be added without degrading yield and reliability, so the only practical way to get to k~2 is to incorporate a single large pore with clever processing as an “airgap.”

A multiyear development effort to create a manufacturable airgap process was led by IBM fellow Dan Edelstein, program manager for low-k CVD BEOL, who provided Solid State Technology and WaferNews with exclusive insight into how they achieved these remarkable results. He explained that unlike previously known airgap process flows, the IBM approach starts with a standard dual-damascene copper and SiCOH dielectric process that has been in production for years. Airgaps are formed using a multi-step etch, using a hardmask patterned with either self-assembling monolayers or standard lithography depending upon the geometry of the interconnect.

Unfortunately, IBM's press release touting the airgap achievement is so grossly hyped that it’s caused severe misunderstanding throughout most press reports on this process. The new technique "skips the masking and light-etching process,” says the official release. “Instead IBM scientists discovered the right mix of compounds, which they pour onto a silicon wafer with the wired chip patterns, then bake it.”

In reality, while self-assembly can be used to make an array of nominally 20nm holes by spin-coating and baking, these holes merely pattern the hardmask that is used to etch the gaps into the dielectric, explained Edelstein. A non-critical lithography step is used to block out circuit areas that do not need gaps, he said. The self-assembly layer is not even used to pattern the hardmask used to make airgaps at upper levels of the interconnect. “At some point in the hierarchy it becomes more viable to use lithography instead of self-assembly,” he said.

While IBM doesn't use airgaps for the first level of metal, they could be used at any of the higher levels within the hierarchical interconnect stack, Edelstein noted. “Most chips won’t need air-gaps on all levels, but perhaps on half,” he said.

No matter the level, a special three-step etch process to form gaps with narrow top openings is the key to this process (see figure). “We etch a narrow channel down so it will cap off, then deliberately damage the dielectric and etch it so it looks like a balloon,” he explained. “You have a big gap with a drop in capacitance and then a small slot that gets pinched off.”

Starting with dual-damascene copper lines/vias and SiCOH single-phase dielectric, the essential IBM airgap process flow is as follows:

1) Deposit hardmask;
2) Spin-coat an imaging layer; either special new diblock polymer or standard photoresist;
3) Create holes using either the self-assembly properties of the diblock or standard lithography;
4) Block out circuit areas to not be etched using non-critical photolithography;
5) Transfer holes from the imaging layer to the hardmask;
6) Etch three-step sequence—first an anisotropic RIE to form deep openings into SiCOH, then plasma damage of the column sidewalls, then isotropic wet etch to remove most of the remaining SiCOH underneath the hardmask;
7) Strip hardmask; and
8) PECVD of the next SiCOH dielectric level to cap the gaps with a classic “pinch-off” shape.

Since the self-assembling mask layer is not aligned to the underlying interconnect structures, and since the block-out mask is “non-critical” to save costs, the hardmask will inevitably expose the tops and sides of some metal lines to RIE. Consequently, the SiCOH etch chemistry needs to have excellent selectivity so as to not attack copper and any metallic barrier layers. Edelstein says that they’ve been able to work with standard gas precursors for this critical RIE step.

The new airgap process is an optional loop off of the standard flow, so designers can choose to use airgaps at any of the levels in the on-chip interconnect hierarchy—and IBM also has developed an automated algorithm for making the block-out mask. “As a customer you can turn on the air-gap option for any level on any chip. We can put the gaps in independent of any incoming design,” Edelstein told WaferNEWS. The ability to add air-gaps as a “drop-in” to an existing on-chip interconnect process flow minimizes risks, and explains the company’s confidence that this flow will be used in manufacturing by 2009.

While the diblock polymer is only one part of this airgap process, it is a significant addition. Chemists at IBM Almaden Research reportedly developed this material for broad applications in fabs—it’s like a standard photoresist in terms of handling and dispensing, it has a wide process window, and IBM has detected no shelf-life problems for up to one year.

Using self-assembly in coordination with lithography opens up new possibilities in general for integrated process flows, so look for news of additional applications in coming years. “We hope that we can use directed self-assembly to get to other device features,” said Edelstein. “This is just the tip of the iceberg.”

— E.K.

Labels: airgap, fab, IBM, IC, interconnect, low-k, self-assebly, ULK

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070504: IBM add airgaps for faster chips

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Ed’s Threads 070129

Musings by Ed Korczynski on January 29, 2007


Intel wins race to be Intel
How did it happen? How could Intel present 45nm transistor results with high-k dielectrics and dual metal gates (HK+MG) years ahead of everyone else? Mark Bohr, Intel senior fellow in logic technology development, stated, “I don’t believe any other company will have high-k and metal gates until the 32nm node or later.” If this is true, it is only because IBM and other companies felt that they wouldn’t need HKMG for 45nm so they did not start manufacturing work two years ago. Thus, Intel has won a very difficult race as the single contestant.

It seems that the company even surprised itself with these results. On Thursday Jan. 25th, the day before the official announcement, Intel invited journalists to a last-minute show-and-tell at its Robert Noyce HQ building in Santa Clara, CA. PCs running on 45nm “Penryn” chips were shown—all of which came from the “first-silicon” wafer with these new materials processed using the first mask-set. Packaged first-silicon chips received at Intel’s Folsom test lab at 1:00 am had functioned, and the team immediately rushed one into a motherboard which promptly booted a software OS two hours later. Intel showed a photo of the team toasting their success with Martinelli’s sparkling cider at 3:00 am—give Intel credit for maintaining entrepreneurial zeal with nearly 100,000 people.

Two core competencies were at work to get to these results: extreme discipline in manufacturing execution, and proprietary design and yield-learning methodologies. Since Intel has always had to live in the brutal merchant market, it has always aimed for the sweet spot in the middle of manufacturing-cost and chip-performance, and then relentlessly driven to meet its goals. Instead of silicon-on-insulator (SOI), Intel pushed traditional planar transistors on bulk silicon wafers to the limits of traditional materials for its current 65nm node manufacturing.

Looking at 45nm options about two years ago, Intel decided to stick with bulk silicon wafers and add HK+MG. In Jan 2006 it announced yielding SRAM TEG chips with >1B transistors, but kept secret that these chips used HK+MG. Still secret is the hafnium-based dielectric composition, both of the metal gate materials, and whether the process flow is “gate-first” or “gate-last.” The new transistors still maintain strain in the channel regions for maximum carrier mobility. Innovative design rules and advanced mask techniques will be used to extend the use of 193nm dry lithography, which we may assume includes orientation limitations in harmony with illumination sources. All these changes result in new process integration challenges and new yield-loss mechanisms, so we might expect it to take a while longer to ramp yield. Amazingly, Intel shows a 45nm yield-learning curve that tracks the last three nodes (see figure, above).

CEO Paul Otellini—dressed all in black like an international jewel thief, perhaps due to having spent excessive time around Steve Jobs—stated, “The plan is to have microprocessors in end-users hands by the end of 2007.”

Meanwhile, with timing that just could not be coincidence, on January 26th SEMATECH announced R&D; of a gate-first HK+dualMG process. “Be aware of the difference between a real manufacturing commitment, and research papers that continue to fall short of these results,” stated Intel's Bohr. The very next day IBM/AMD/Sony/Toshiba said that they will use HK+MG with their 45nm transistors sometime in 2008. We may assume that this announcement was rushed out in response to the Intel press release, since it erroneously refers to HK+MG as a single material—either the IBM alliance plans to use only one of the two, or IBM needs a technologist to review their press releases.

Technology development continues in the industry. Intel’s use of HK+MG materials in mainstream 45nm commercial manufacturing is certainly a significant milestone. Certainly other companies will follow, though in their own ways and in their own times. Due to the extreme complexities involved in any nanometer-era IC manufacturing, it’s getting more and more difficult to compare results from different companies. Fortunately, you can trust SST and WaferNEWS to sort the reality from the hype.

— E.K.

Labels: 45nm, high-k, HK+MG, IBM, Intel, metal gate, semiconductor

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070129: Intel wins race to be Intel

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