Ed’s Threads 080613
The last musings in this blog on Friday the 13th of June, 2008

Process integration drives the IC industry
The next 10 years will witness more changes in mainstream manufacturing technology for ICs than in the last 40 years combined. An industry based on “what have you done for me lately” can never rest on its laurels, and so innovation must continue, despite limits in 2D scaling. With rapidly escalating costs projected for 32nm node and smaller digital CMOS manufacturing, it is inevitable that IC companies look to analog, packaging, and heterogeneous integration to add relatively greater value for lower cost and risk. Unique process integration challenges at each fab will drive everything for the next ten years, as shown recently by presentations at the recent International Interconnect Technology Conference IITC., some of which I've already discussed in this blog.

What are the ramifications of all of these subtle changes? With basic “unit-process” building blocks fairly well established, it is likely that the only fundamentally new tools to be developed will be for metrology. The current generation of thin-film, lithography, and thermal processing tools are extremely productive and should continue to be used with modest evolutionary upgrades over the next 10 years. The only exception to this is probably EUV lithography, which is still under development but shows promise.

New integration of old processes can be seen in the evolution of barrier layers for Cu metal in dual-damascene structures. At IITC, Novellus showed that PVD Ti/TiN is the newest Cu barrier to replace Ta -- though Ti is the standard barrier for Al metal lines it was replaced by Ta when the industry first began using Cu lines. Though less expensive than Ta, Ti can react with both fluorine (in FSG dielectric) and Cu and so was not considered to be an acceptable barrier. However, now that FSG has been replaced with SiOC in many fabs, a 5nm thin TiN layer (formed with 50 at% N) capping on Ti stops Cu diffusion. An ultra-thin PVD Ti wetting layer on top of the TiN provides a good surface for ECD fill of Cu.

NEC has targeted high-reliability automobile MCUs, and examined PVD Ti/Ru barrier metal for these applications. After 7 hours at 350°C, Ti diffuses into the Ru, but no Cu diffuses through the Ti. PVD-Ru with (001) orientation can be removed by CMP using conventional slurry for Ta/TaN removal. The Ru barrier achieved 12% lower resistance than the conventional Ta type barrier for 70nm wide Cu lines, while time-dependent dielectric breakdown (TDDB) was unchanged. The Ru/Ti barrier shows 35× longer lifetime (T50) than Ta/TaN. Whatever process is finally developed will run for over 10 years with essentially no changes, as per the supply contracts to the auto industry. I toured NEC Roseville recently and saw old 200mm tools being installed with plans to run for >10 years using ≥150nm node processes.

Low-k air-gaps are also great examples of using old unit-processes in new ways, since CVD oxides (SiOx and SiOC) and spin-on polymers already well developed will be used, while established lithography and etching technologies will complete the integration. EDN's Ron Wilson covered many of the latest air-gap integration details from IITC in his fine blog, but the most important consideration is that no new manufacturing tools are needed to make them happen. Designs may need to be tweaked, and the process integration will be challenging, but this approach is relatively low-risk and may be integrated into older fab lines.

Further proving that “there is no more noise (…there is only signal),” IMEC’s Michele Stucchi at IITC examined the effects of inherent line-edge roughness (LER) and via misalignments on the Efield and electrical breakdown between wires. An enhanced electrical field between adjacent lines is induced by LER-induced reduction in spacing. Compared to a nominal electrical field between lines with zero LER, a probabilistic analysis results in enhancement to the field, which can be a factor >2 in 30nm spaced lines. For wires with 30nm spacing, Efield may be high enough to guarantee at least one bridge in 20μm of line length. For via misalignment of 10nm in standard dual-damascene structures with 30nm spacing, the field enhancement can be a factor >3.

An amazing example of tricky process integration to eliminate variability in lithography was shown by Matthew Breitwisch of IBM, in describing work with Macronyx on phase-change memory (PCM) technology. Ge2Sb2Te5 (GST) was the first material investigated which changes from a high-resistance amorphous structure to a low-resistance crystal at ~170°C. A PCM cell is made up of a variable resistor in series with an access device (which may be a diode, BJT, or FET), and current flux near one million A/cm2 is needed for a few nanoseconds to create the change. To concentrate the current in programming, uniform small pores are achieved using a key-hole (a.k.a., “pinch-off CVD”) process:

- blanket oxide, hardmask and nitride depositions,
- lithography,
- anisotropic etching through the dielectric stack,
- an isotropic oxide etch to create an undercut below the hardmask, and
- conformal polysilicon CVD to form consistent 43nm wide keyholes.

The keyhole widths are controlled by the oxide etch and the poly CVD, and not by the lithography, such that equally sized pores form in the middle of line spaces of varying width…all without any new unit-processes.

With razor-thin process windows and systematic process-design interactions, each fab may have to optimize its own integrated process flow. If each fab runs a unique flow, then a mask-set run on one line will yield very differently on a second line, and this reality may create problems for companies trying dual-sourcing with foundries.

New materials and evolutionary upgrades to old materials will continue to support new integration schemes in fabs, while most of the tools will remain the same. However, OEM applications labs will run non-stop as fabs try new designs-of-experiments (DOE) for new integration schemes. It will be increasingly difficult to get process information out of fabs, since each line will have to be set up with unique tricks and integration schemes. Designers will have to really start innovating, as digital CMOS shrinks no longer guarantee lower cost and higher performance.

There will be many IC types that will probably never be designed at the 32nm node. A friend working on a graphics processing chip explained to me that they needed to go to 65nm to get a speed improvement for their target application, but their modeling shows that additional speed will now provide no user benefit. Going to 45nm adds huge design costs and manufacturing yield risk, and so they now plan to stick to 65nm but work on cost and power optimization in re-design. Their next 65nm chip may use 3D interconnects or integrated passives for improved performance, however, so innovation will continue… just in new directions. Such is the blessing/curse of “living in interesting times.”

Henceforth, my challenges will be elsewhere. This is my last blog post on my last day as a Technical Editor for Solid State Technology magazine; I am resigning to pursue other interests, first of which will be an immediate 8-week sabbatical. When I return, I will probably work for the semiconductor manufacturing industry, in an as-yet undetermined capacity that doubtlessly will be "interesting." I thank PennWell Publishing for years of rewarding employment, and wish the company well. Special thanks to James Montgomery, who diligently and masterfully copy edited most of these 76 postings.

—E.K.

Labels: 32nm, 3D, airgap, CMOS, copper, IITC, integration, interconnect, process, research

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080613: Process integration drives the IC industry

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Ed’s Threads 080225
Musings by Ed Korczynski on February 25, 2008

Interconnect technology mature
On-chip interconnects made primarily of copper metal insulated with SiOC low-k dielectric material are the current state-of-the-art for the commercial IC manufacturing industry. A report from the TECHCET Group quantifies the materials that are forecasted to be needed to form interconnects for 65nm to 32nm node ICs. Except for some new barrier layers, the only major change on the interconnect horizon is the use of pores or air-gaps in the dielectric material to get to ultra low-k (ULK, a.k.a. extreme low-k or ELK).

Though carbon nano-tubes (CNT) have been considered as new conductors, and self-assembled dielectrics have also been investigated, commercial IC fabs are necessarily slow to change proven technologies, and so it is almost certain that these newer approaches will not be used for commercial IC manufacturing anytime soon.

From first principles and reasonable modeling, we know that Cu is not the ultimate electrical conductor, but lacking room-temperature superconductors and ways to form dense arrays of metallic CNTs, the only near-term solution is to use more and more copper layers as a method of dealing with higher resistance copper in smaller lines. With Cu pushed to the limits, it is axiomatic that current density inside minimum pitch lines is huge such that electromigration induced reliability problems are inherent.

Cu lines in advanced dual-damascene interconnects are already complex structures, with barrier layers to prevent Cu diffusion into low-k dielectrics. An ideal Cu barrier inhibits electromigration, though any barrier is more resistive than the Cu itself, so it should be as thin as possible to minimize resistivity without allowing for Cu diffusion. For the 32nm node, Copper Manganese (CuMn) and Ruthenium barriers have been investigated, in part due to the integration advantage of being able to electro-plate Cu directly on either barrier without the need for a PVD Cu “seed” deposition. If CuMn is used, then some of the Mn diffuses to the surface of the Cu during metal anneal, and removing this surface Mn during the CMP step results in lower via resistance due to a direct Cu-to-Cu bond.

For cap layers, silicon nitride has been used at ≥90 nm, but it has a rather high dielectric constant of ~7, so SiCN with a dielectric constant of ~5 has been used at 65nm. For 32nm the most likely capping barrier may be CuSiN—formed by reacting the post-CMP Cu with SiH4 and NH3—or CoWP.

Dielectrics technology has never met the wishes of the ITRS for a different material for each node. With the k-value stuck at ~2.7 for a blanket SiOC film, the only practical solution to lower k has been to substitute “air” (a low-pressure vacuum, really) as part of the dielectric material. The air can be in random zero-dimensional “pore” (or nanopore) structures in the material, which may be formed by sublimating the homogeneously-nucleated 2nd-phase of a deposited blanket film. The air can be in random or ordered one-dimensional “air columns” in the material, as shown by Edelstein et al. at IBM. The air can also be in patterned two- and three-dimensional “air-gaps” formed by many different process flows, as shown by Hoofman et al. at Philips/NXP.

Conformal dielectric CVD processes can also be tuned to automatically form air-gaps between lines—known as “key-holes” or “bread-loaves” due to the characteristic shape of the gap when viewed in cross-section—for metal line spaces of a certain pitch. Standard dielectric CVD processes are tuned to avoid air-gaps in random line spaces so that gaps do not appear spontaneously in some portions of a random IC design. Key-hole air-gaps as desired dielectric structures were first reported by Shieh et al. of Stanford in the pages of SST in 1999, and the major limit with their use has been the need to impose design constraints on metal line pitch.

However, it now appears certain that nearly all 32nm node ICs will be made with restricted design rules just so that lithography will work. Likewise, CMP and Etch uniformity specifications at 32nm seem to mandate severe restrictions on geometry and the extensive use of “dummy fill” beyond all precedent. If a design must already deal with such limitations, then why not integrate in key-hole air-gaps by CVD? Alternatively, like IBM or Matsushita, you can use a non-critical lithography masking step and etching to define the air-gap locations independent of line pitch.

Lest we forget, aluminum metal is still used as the on-chip interconnect for some 65nm node memory chips. Proven process technology is replaced only when IC performance mandates a change, and so evolutions happens far more often than revolutions.

—E.K.

Labels: copper, dummy fill, interconnect, low-k, ULK

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080225: Interconnect technology mature

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Ed’s Threads 070928
Musings by Ed Korczynski on September 28, 2007

Who needs through-silicon vias?
Besides MEMS and opto-electronics, who really needs through-silicon vias (TSV) for commercial ICs? This was the burning question around which presenters danced for an afternoon at the International Wafer-Level Packaging Conference (IWLPC) held this September in San Jose, California. Starting with IC and wafer-level packaging technologies already in use, experts seem confident that technology integration can create a manufacturable TSV fab flow. However, while 3D-WLP is already commercially viable (pun intended), TSV do not seem to be needed for the near future; wire-bonding already can handle up to 16 chips, and 2 level connections can be easily flip-chipped for high-performance (like for a microprocessor cache).

Ken Gilleo of ET-Trends LLC discussed the “coming paradigm shift in packaging” caused by TSV and wafer-level packaging, asserting that significant technology development has occurred with unit processes in recent years such that the main technology hurdles remain with integration.

Leslie Lea, CTO and deputy CEO for STS, explained how deep reactive-ion etch (DRIE) for TSV on 300mm wafers will still use a derivative of the sequential “Bosch Etch” process, using the C4F8 plasma for polymer sidewall deposition, then SF6 plasma for etching. This process can produce vias to 80:1 aspect ratios, but sidewall scallops inevitably exist. Cu-TSV plating time shown was 4 hr for 50µm via, while 10µm via filled in 1 hr using NEXX systems and Enthone chemistry to create via fills without voids—with vias of 10-50µm depths all nicely filled on the same chip.

TSVs have been demonstrated in four different approaches and integration schemes: blind, poly, tungsten, and copper. Jim Walker, research vice president for Gartner Dataquest, suggests that we all should use the standard PCB term “blind vias” for essentially the same structures in silicon. Unlike the other three, ‘blind’ vias don’t include the conductor, but etch/drill out openings through an upper silicon chip, typically to allow a wire bonder to make connections to bond-pads on a lower silicon chip.

These are not new. Back in 1989 I developed a pilot process for a 3-level WLP using blind TSVs for an accelerometer chip for SenSym (Analog Devices’ designers were much smarter and their planar chip design was far more manufacturable and lower cost, so sadly for me at the time the chip was killed at pilot). Blind TSVs can be combined with flip-chip stacks and C4/C4NP bumping to get to three or more silicon layers with relatively low cost and minimal disruption of current packaging flows.

Blind TSVs are another way that wire bonders may continue to function as the ‘work-horses’ of packaging lines, working with KOH or EDPW wet-etches to form sloped openings along the crystalline planes in silicon. In an exclusive meeting with WaferNEWS, Giles Humpston, director of R&D for Tessera, explained that the company’s ~$100M investment in optical-WLP technology built on the acquired ShellCase technology for blind TSV applied to the unique requirements of image-sensors and quartz substrates.

Filled vias with poly, tungsten, or copper are the TSV ideal that many of us have conceived of for 3D ICs. If design and test software could handle it, and if integration can be as low as $200/wafer (EMC-3D goal), then these TSV might be first used to stack like devices like memory parts. Phil Marcoux, longtime packaging technology expert currently with Chip Scale/TPL Group, thinks that full integration won’t be ready for five years. Gilleo countered that in 2008, “some memory will use TSV.”

Citing first principles of electrical interconnection—going back to the use of copper in the first US printed circuit board patent in 1902—Gilleo is convinced that ultimately copper is the way to go for filled TSV. Used both for PCBs and on-chip interconnects, there is a tremendous amount of proven technology that can be borrowed to speed up TSV integration. “It’s well controlled in electroplating, and it has the right balance of chemical and mechanical properties,” informed Gilleo. It becomes the nature selection for the conductor. “It has almost everything you want for building conductor pathways.”

All of this was known to the early pioneers of the planar IC at Fairchild Semiconductor. And yet they chose aluminum over copper, because copper is more reactive and can more easily diffuse into silicon and damage transistors. Copper will always have a much higher expansion with temperature compared to silicon, and so high-temperature processes will inherently stress barrier layers. Polysilicon can be annealed and then have the same expansion with temperature as the silicon wafer. Of course, polysilicon conductivity is always lower than copper, so there are trade-offs in the TSV conductor choices.

While debating whether to consider integrating poly or copper or even tungsten plugs, a gold wire bonder has already made the connection. Packaging moves fast.

--E.K.

Labels: 3D, blind TSV, copper, IC, interconnect, stack, through-silicon via

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070928: Who needs through-silicon vias?

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Ed’s Threads 070608
Musings by Ed Korczynski on June 08, 2007

IITC 2007: Airgaps & chip-stacks
Airgaps and 3D-stacks were the big news from the 10th International Interconnect Technology Conference (IITC) recently held near the San Francisco airport. Two major new materials was presented—IBM showed rhodium (Rh) electro-chemical deposition (ECD) for ≤32nm contact plugs, and Fujitsu showed nano-clustered silicon (NCS) with low k=2.25 for a dielectric—but most new work involves the same materials combined in clever new ways. Airgap technology was covered in four oral presentations, three posters, and countless informal hallway discussions.

Dan Edelstein, IBM Fellow and manager of BEOL technology strategy at Yorktown Heights, NY, gave an invited talk on the many integration challenges for 32nm node interconnects, including resist poisoning from low-k outgassing, low-k damage removal, and the need for improved thin-film interfaces. “We need to keep adding innovation just to stay on the trend-line,” he commented. For example, the industry has historically seen chronically low SiCOH low-k adhesion on SiCHN barrier layers—regardless of equipment, CVD precursor, or plasma preclean—due to a carbon-rich initial deposition. Adding a diverter-valve to the tool allows for stabilized precursor flow before RF power is turned on, which eliminates the carbon-rich deposition and thus solves the adhesion issue. With subtle integration challenges such as these, IBM has chosen to add airgaps as a side-loop with no new materials, tools, or baseline processes. Airgaps drop k by ~35% for any given dielectric material, Edelstein noted, adding that IBM has “shown this on gapped SiOF and low-k SiCOH, and will do it next on ULK porous SiCOH.”

The IBM airgap process both removes and re-deposits some dielectric material, while most airgap approaches for logic chips rely on removal processes alone. The Crolles2Alliance (CEA-Leti, Freescale, NXP, and ST) uses SiO2 at line-levels and a polymer for the via-levels within the dielectric stack, then HF vapor or wet-etch-chemistries to remove the SiO2. NXP and Dow Chemical showed removal of a thermally degradable polymer (TDP) through a CVD SiOC cap layer to make ~30% airgaps at M2 as part of a keff ~2.5 to hit 32nm node specs.

The Crolles2Alliance also showed some of the integration tricks needed to use porous ULK dielectrics at the 32nm node. Different plasmas may seal pore surfaces to provide barrier properties for long-term reliability: CH4 adds C, NH3 substitutes N for C leading toward SiON compositions, and He/H2 plasmas retain near original stoichiometry. Though Cu bulk resistivity is only ~2.2 µOhm-cm, for 60nm line widths it is ~2.9 and increases with reducing widths. CMOS32 uses 50nm Cu line widths for M1, requiring a self-aligned barrier (SAB) <4nm for EM performance, an ALD barrier and thin-Cu seed for filling, and either a CuSiN or CoWP cap layer.

NEC research labs showed that direct ECD of Cu without a Cu-seed layer provides larger grain size and higher Cu(111) orientation. Damascene structures were first sealed with TiN, then either Ta/Cu or Ru layers were deposited. The TiN barrier layer is definitely needed beneath Ru to block Cu diffusion into the dielectric. Ru PVD using DC magnetron sputtering with Ar gas at room temperature produces high orientation of Ru(002). Since Ru(002) is hexagonal-close-packed, it matches well with the preferred Cu(111) face-centered-cubic orientation such that 40%-50% can be grown directly on Ru in dual-damascene structures. Some day, metal line specifications may include not just dimensions and resistivity, but grain orientation and size-distribution too.

Ibaraki U. and Hitachi presented research showing that higher chemical purity leads to lower resistivity in Cu lines. Increasing both the Cu anode purity from 4N to 9N along with the CuSO4·5H2O purity from 3N to 6N reduced line resistance by 21% in 50nm wide lines, with all other process parameters held constant. The high-purity process increased the average grain size from 70 to 74nm, and significantly reduced the oxygen content in the final annealed Cu lines to <1 wt% from the previous 3-4 wt%.

Based on first principles of thermodynamics, an alloy of Cu/Mn can be annealed to result in self-segregation of Mn to the dielectric/Cu barrier. One fundamental advantage of this process is that no barrier is formed at the bottoms of vias, which minimizes resistance. Toshiba’s R&D; group tested self-aligned Mn barriers with 244-via-chain structures and found one-third the resistance compared to Cu vias using the standard Ta barrier.

Georgia Tech and U. of New Mexico researchers showed that a 60% increase in the total number of wire levels is sufficient to account for ~5x increase in the resistivity of wires. Careful routing and a logical hierarchy seem to go a long way, but eventually the industry must get serious about 3D ICs using chip-stacks.

Patrick Leduc of CEA-Leti provided an overview of the main challenges to realizing high density 3D ICs: bonding with ±1µm alignment at T<400°C, Si thinning to <15µm, and through-silicon via (TSV) diameters <3µm. Thermal management issues may not be too difficult—assuming each transistor contributes 0.7W to a 50 W/cm2 average—since bulk silicon acts as an efficient heat spreader and the metal lines conduct well.

Freescale’s Scott Pozder explained that EDA software tools may be the current biggest limitation to 3D integration, since standard tools cannot even account for metal levels on multiple chips. If you explicitly design for 3D, then models show that multiplicative yield-losses can be avoided or eliminated.

There were ~480 conference attendees this year (plus several hundred additional folks running evening supplier-seminars and exhibit booths). Among the attendees with whom I enjoyed discussions were (in alphabetical order) Al Bergendahl, Chris Case, Paul Feeney, Terry Francis, Mike Fury, Xiao Hu Liu, Steven Luce, Satya Nitta, Mike Shapiro, and a special appearance by casually retired Mike Thomas.

—E.K.

Labels: airgap, copper, dual-damascene, IITC, interconnect, low-k, self-aligned barrier, ULK

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070608: IITC2007 airgaps & chip-stacks

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