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080317: There is no more noise...
Ed’s Threads 080317 Musings by Ed Korczynski on March 17, 2008
There is no more noise...
There is only signal. In controlling the manufacturing processes used for advanced nano-scale IC, the aspects of metrology which we used to be able to ignore as “just noise” are now essential signal we must control. Where to draw the line, and how close is close are just some of the challenges in ensuring that data streams become productive information for fabs. Metrology sessions at SPIE this year shone fractional wavelengths of light into the darkness of controlling accuracy, too. When IC features were greater than the wavelength of light used in photolithography—and likewise much greater than a countable number of physical atoms—there were many aspects of manufacturing which we could simply ignore. With the smallest IC feature, typically defined by the minimum half-pitch spacing between lines, now reaching ~45nm (which is less than one-quarter of the 193nm wavelength used in litho) we now experience “second-order” and “third-order” effects which must be controlled. Vladimir Ukrainstev of Veeco Instruments co-led a panel discussion at SPIE 2008 on the need for CD-SEMs to be accurately calibrated with 3D-AFMs. Researchers have reportedly seen a mere 1° change in the sidewall angle of a device structure result in a 2nm change in the CD measured by a standard 2D SEM. With the allowable budget for CD variation shrunk down to 3nm-4nm, this sidewall angle dependence must be controlled. The greatest risk is in process drift in an etch chamber, where sidewall angle can change spacially (e.g., from the center to the edge of wafers) or temporally (from wafer to wafer over time), which can induce substantial error in the CD-SEM measurement. With tight feedback loops in advanced fabs, erroneous CD-SEM data can be mistakenly used to set the wrong etch parameters for following lots, which can degrade yield. “Instead of changing CD etch time by the week, we’re changing by the lot or the wafer as part of APC,” explained Kevin Heidrich, Nanometrics’ senior director of new business development, in an exclusive interview with WaferNEWS. Total CD control is ~4nm for all variability; a normal rule of thumb for precision over tolerance is 0.1, so the total budget for metrology is 0.4nm. All measurement techniques are subject to some error, and even the best 3D-AFM is still subject to tip-wear and calibration. Veeco has been working with 3 rd-party specialists to optimize AFM tips for different applications, with great results reported for various shapes nano-machined from single-crystal silicon for strength and then coated with some manner of a carbon coating for wear-resistance. NIST showed SPIE attendees this year that even with a slow, expensive, and destructive technique like TEM, there is still 0.33nm (standard deviation, 1σ) of the sidewall angle uncertainty. Everything else adds up to 0.63nm of total uncertainty. Calibration is vital to minimize the propagation of uncertainties. One of the issues in determining the side-wall angle is what portion of the sidewall to include in the analysis. For features with corner rounding, this could be challenging even with ideal 90 degree sidewalls. Just considering 2nm radii of curvature on the top corners of etched polysilicon lines of 32nm to 45nm widths, and ~10% of the linewidth varies with where a CD-SEM draws the line for the edge. To help control APC in all manner of deposition and removal processes, Nanometrics recently announced the delivery of the company’s 1000th integrated metrology sub-system; the milestone system was integrated into an advanced plasma etch system used to control gate CD in advanced logic devices. At SPIE, IBM (Daniel Fischer et al.) showed OPC requirements for 32nm and the metrology tool calibrations need to support this advanced node. Modeling calibration sites per mask level has increased dramatically: normalized to the 90nm node, 65nm had 10×, and 32nm is 100×. There are now multiple CDs per contour, which results in a reduced number of measurement sites per wafer. For tool calibration, fundamental parameters of magnification, rotation, etc. each must be properly considered in modeling. The researchers showed that scanning a line array in orthogonal directions in a CD-SEM induced up to 2% variation in measurement due to the beam’s oval shape. It’s not noise anymore. “The users must understand the measurement techniques and have them constant or have a consistent offset to be able to use the data,” said Fischer. He added that with real device structures, 144nm was seen by a 2D tool while 160nm was measured by a 3D tool, so some manner of rigorous automated edge-detection is essential. OCD looks very extendable to finFETs, too. SEMATECH and KLA-Tencor presented a paper on metrology for high- k finFETs at SPIE. Using high- k HfSiO thicknesses of 1.5nm and 3nm over Si 3N 4, and using TiN as the metal gate, a thorough DOE of depositions over fins was done. Then using KLA-Tencor's next-generation spectroscopic ellipsometer (measuring 225nm and up) for OCD, and CD-SEM from AMAT and also HR-TEM, cross-checks between the OCD and standard thin-film measurements showed that the offset was ~1nm. For the metal gate measurements, it was found that the TiN optical properties varied due to what is suspected to be some manner of slight oxide formation. Data from dense arrays showed serious offset from the pad areas, so correlations must be considered. Measuring in the fin area seems to provide sufficient resolution for process control for both the high-k and metal-gate depositions. OCD measurement precision was at the 1% level or better, and in good agreement with reference measurements. OCD looks very promising for finFET gate stack characterization. n&k Technologies has modified the optical path of their spectroscopic ellipsometer tool to add a pinhole lens which narrows the transmitted beam spot size from 400μm to 50μm. Since real-world ICs and photomasks tend to have designed areas with regular 50μm arrays, this opens up the ability to measure many more real structures. Collecting the reflectance and transmission in both s- and p-polarizations using 50μm spots provides four separate signals to be used in determining all the layer thicknesses on the mask, including quart etch dimensions for phase-shift masks. In pushing the limits of signals, IBM and Hitachi recently announced a unique, two-year joint semiconductor metrology research agreement for 32-nm and beyond characterization and measurement of transistor variations. Engineers from the two companies and Hitachi's subsidiary, Hitachi High-Technologies, will conduct joint research at IBM's Thomas J. Watson Research Center in Yorktown Heights, NY and at the College of Nanoscale Science and Engineering's Albany NanoTech Complex. Combining individual research strengths and IP will help " reduce the significant costs associated with research needed to advance the next generation of chip technology," said Bernie Meyerson, VP of strategic alliances and CTO for IBM's systems & technology group, in a statement. Rudolph Technologies has become the first OEM to join SEMATECH's Metrology Program headquartered at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany. The initial program addresses a range of issues, including the metrology of thin films and metal gate stacks; wafer front, back, and edge macro defect inspection; and inspection and metrology for through silicon vias (TSV) and three-dimensional integrated circuits (3DIC). -- E.K.Labels: accuracy, CD, fab, manufacturing, metrology, noise, SEM, semiconductor, SPIE
posted by [email protected]
080317: There is no more noise...
080111: Flood of used 200mm tools
Ed’s Threads 080111 Musings by Ed Korczynski on January 11, 2008
Flood of used 200mm toolsSemico Research, working with affiliated Semiconductor Partners, has released a new study of the near-term forecast for used 200mm wafer processing tools soon to flood the market. In addition to identifying companies that are likely to either purchase or sell a fab and their expansion or divestiture plans, this study includes five-year device forecasts by technology node and detailed wafer demand. The market for used equipment is expected to grow from $300 million in 2007 to more than $8 billion in 2009. "As leading edge digital memory and logic manufacturers build 300mm fabs for process technologies of 65nm or less, this will obsolete their 200mm fabs at 130nm or 90nm and some of their 300mm fans at 90nm. Analog and mixed signal manufacturers will have a need for these fabs to meet for expansion to satisfy the growing analog, mixed signal, and RF markets," explained Morry Marshall, Partner, Strategic Technologies at Semiconductor Partners. The number of used tools forecasted in this study may be estimated by considering the average selling prices (ASP), and this varies widely depending upon tool categories. Tom Cheyney’s well written recent ChipShots blog mentions the standard 10%-20% cost of new tools, which certainly has been the historic average. Unfortunately, we’re entering into a new era where the lessons from history may not hold. The upper limit of used tool sales prices comes from unique specialty process tools, needed to expand capacity on existing lines, which are no longer sold new. Like a legendary musical instrument (e.g., Fender Stratocaster pre-CBS electric guitar, or Selmer Mark VI saxophone) with only so many made, any still working are highly functional, and if you’ve built your business using them you’re willing to pay a premium price to keep using them. In the last year, I have heard of rebuilt 150mm tools with warranties selling for >$1.5M. In some cases this could be >200% of what had been the new sales price. The lower limit of used tool sales prices comes from mainstream memory and logic fabs lacking uniqueness in the toolset. Since the used-tool ASPs are primarily determined by the supply/demand balance, a supply glut can lead to what-the-market-will-bear prices below 10% of new. If a seller tries to hold out for a more "reasonable" price only to find no takers, the line has to be shutdown and sold "as is" for even less money. A working fab is a proven thing. There is risk in shutting down, decontaminating, shipping, and re-setting up a line, but at least if you start with a working line you have some baseline reference. A shuttered fab is full of extra risk. Every process chamber must be re-checked and proven; every gas line feeding every tool is now suspect. How much is a shuttered line worth? About two years ago I spoke with the general manager of a Chinese fab about used 200mm toolsets and supply and demand. He told me that he’s routinely approached by people wanting to sell lines for ~US$50M, and he tells them to not bother him until the price drops to $25M. So who might be buying used 200mm lines? The Semico report mentions the general truism that, "Production of some device types, such as discretes or MCUs, will not move forward appreciably to more advanced technology nodes." MEMS and discrete chips have been produced in recent years primarily on 150mm silicon wafers, but STMicroelectronics and Freescale now like 200mm silicon wafers for dedicated MEMS production. MCUs for appliances, automotives, and general industrial applications may be industry entry points for new IC fab companies based on China (and eventually India, after infrastructure issues are eventually resolved). Philips likes 200mm for integrated passives and MEMS for advanced packaging, primarily through "PASSI" branded passives integration. So there is certainly demand. But the lingering impression is that it won’t keep up with the supply glut, and it will be a classic "buyer’s market." A recent example of this dynamic is Atmel's sale of the 200mm tools in its North Tynesides, UK fab last year. Atmel originally tried to sell the entire facility to a company that would keep the line running in the UK. Leading broker of fabs Colliers ATREG was retained to try to make a deal happen with the constraint that there was "no opportunity to acquire the tools separately." At the end, TSMC bought the tools only for $82M, with expectation that they will add capacity in Shanghai, China. The Semico report forecasts the value of available used equipment for the next four years (2008-2012) to be $5.4B, $8.2B, $6.5B, and $3.9B, for a total of $24B in value. For ASPs of ~15% of new prices, the corresponding equivalent in new tool sales value would be $160B. A rough guesstimate from these numbers would seem to imply >100 fabs with ~20k wspm at 0.13-0.25μm minimum linewidth capacity will flood the market over the next four years. For relative scale, with the SEMI Silicon Manufacturers’ Group forecasting ~10B square inches of silicon being processed for semiconductors each year, this translates into >800 fully loaded fabs globally running wafers in 200mm-equivalents. With 20-40 extra fabs for sale each year, it seems certain that used tool ASPs will have to drop and the revenues to sellers and brokers may not be as high as forecast. Regardless of ultimate pricing, all of these tools under consideration are highly productive (most are still currently cranking out production) and most will eventually find a home. The industry may be able to use most of these tools to manufacture MEMS, discrete devices, integrated passives, and silicon interposers. If a used 200mm tool glut floods over to mainstream CMOS, however, then it could permanently disrupt global pricing for MCUs and other logic ICs. —E.K. Labels: 200mm, fab, flood, forecast, semiconductor, used equipment
posted by [email protected]
080111: Flood of used 200mm tools
071012: Managing mature fabs
Ed’s Threads 071012 Musings by Ed Korczynski on October 12, 2007
Managing mature fabsAssociated with SEMICON Europe 2007, the Fab Manager’s Forum gathered representatives of Europe’s semiconductor fabs to discuss operations of primarily mature fabs. Michael Lehnert, of Renesas Semiconductor, presented examples of the benefits derived from fault detection besides yield improvement in mature fabs. Renesas Semiconductor Europe Landshut (RSEL) has a 200mm line with 13-15k wspm running 0.5 to 0.15 µm for MCUs (the line was originally a DRAM line). Fault Detection and Classification (FDC) is a challenge for a fab running several hundred products, with 10 to 100 parameters/tool resulting in up to 5 GB/day of data. With 300,000 SPC charts and 10 entries per chart, and with the data normally distributed and applied 3-sigma limits with a 0.3% false alarm rate, a fab must handle ~1000 false alarms every day. Manufacturing engineers need to change how they work, spending more time with abstract analyses looking at computer screens, and less time crawling through the fab poking at tools. Monitoring facilities parameters such as gas flows and pressures may provide additional relevant data streams. FDC improvement in wafer-scrap yield was expected, but an additional benefit has been in engineering productivity, with gathering time reduced and more accurate data. Spare-parts and consumables evaluation is now easier, so there is greater confidence in being able to change to less expensive sources when possible. Greater confidence allows for reduction in sampling frequency and reduces the need for dummy wafers. Better preventative maintenance (PM) planning—for example monitoring the filament current in an implanter—results in reduced consumables costs, equipment uptime, and even turn-around time (TAT) due to greater tool availability. Dr. Detlef Nagel, Sr. Director Product Engineering, Qimonda Dresden discussed how to manage APC in worldwide DRAM fabs. Future business requires an evolution from APC to predictive process control (PPC), which will in turn require a revolution in data-mining, multi-variate control, and yield prediction. Technology complexity can be kept under control by generic run-to-run (R2R) controllers and virtual metrology. Qimonda uses SMIC and Winbond as foundries to balance production, along with their own fabs in Europe, the US, and Malaysia. Fast distribution of knowledge is a problem due to regional cultural differences, and the inherent difference between development and volume fabs. One innovative solution is the use of a network of senior equipment engineering specialists, with individuals responsible for an assigned toolset within some areas of expertise. This worldwide captive network improves equipment throughput and reliability at Qimonda fabs; there is traditional information exchange with the foundry partners but not the expert knowledge. Peter Schaffler, global yield enhancement manager for TI, talked about yield enhancement in the Freising fab. It was originally a 3” Bosch fab, and has been continually upgraded to the current level of 0.2µm processing on 200mm wafers; the line runs CMOS/BiCMOS with 20k active reticles used on 400k wafers/year. TI now does tool qualification with product wafers, challenging costs and tool availability. Sampling strategy directly affects your costs: too much wastes expenses, while too little guarantees lost yield. Typical these days is 10-20% of lot starts, but sampling frequency should be determined by the number of lots at risk and the complexity of the mask level, which results in tool-specific dynamic sampling. Or course, an efficient data analysis system is needed to provide macros for data drill-downs using tool, parametric metrology, final electrical test, and other data sets. Proper charting and visualization in an interactive GUI allows new analyses to be done. Single-wafer tracking allows for the extraction of yield-loss signatures like the wafer number in the lot, first or last wafer effects, and different lots with single wafer excursions. For example, electrical-test data that may originally show no signature can be sorted to obtain a clear clustering of parameters into groups of five wafers, which in turn could point directly at a TEL furnace which was the only toolset running batches of five. A breakout session on the dynamics of the used equipment market provided a fantastic perspective on the status of the current market. In addition to third-party brokers, OEMs now provide refurbished tools with full one-year warrantees for typically 40-80% of the original selling price. As always, the price is set by markets: the price to acquire the tool, cost to properly refurbish, and the customer demand for the tool. At the high-end of pricing, the used tool is sold with all new tool specs and it may then be considered as almost just another new tool for capacity. If the market forces align in certain ways, even a used 150mm tool may be sold for US$2M. If you buy through a broker, it is somewhat common to then have to purchase a use license (often for the software) from the OEM. These licenses can range from $10k to $700k for complex tools; and are the single greatest hurdle for customers of 3rd-party brokers. The consensus was that licenses are not unreasonable in principle, but customers really expect to receive some value in terms of software upgrades and service support for their payment. Service-contracts from OEMs certainly minimize the risk of working with used or refurbished tools, regardless of the seller. Hallway discussions with equipment brokers revealed that they’re tracking a tremendous number of 200mm tools which are planned to be decommissioned over the next 1-2 years. How the industry will absorb these tools remains to be seen, but with SECS/GEM interfaces and modular sub-system designs, it’s likely that most of these tools will remain productive somewhere in the world. --E.K. Labels: Europe, fab, mature, OEM, semiconductor, tools
posted by [email protected]
071012: Managing mature fabs
070727: Working together to reach nirvana
Ed’s Threads 070727 Musings by Ed Korczynski on July 27, 2007Working together to reach nirvanaSEMICON West hasn’t been a “selling show” (i.e., a tradeshow where you actually sell stuff) for well over a decade, so why do people still bother to attend it? There are still endless meetings and seminars and panel discussions that provide vital connections and information to keep the industry going. Manufacturing ICs with minimal dimensions below 45nm creates technical challenges that combine with consumer-market challenges to create extreme rewards for success and extremely expensive penalties for failure. For any IC fab company to succeed in the future, partners will be needed and new ways of working together will have to become new habits, as detailed in two separate panel discussions held on succeeding days by Praxair Electronics and DuPont Electronic Materials. The first few decades of the semiconductor industry were based on vertical business integration like that championed by Henry Ford at the carmaker's Rouge Plant, where controlling the stream of raw materials and custom-built equipment resulted in massive economies of scale. Vertical organization under a strong top customer leads to a clear hierarchy of power, and corresponding norms of one-way information flow, dual-source strategies for all suppliers, and limited motivation for fixed relationships. By the 1990s, however, the global semiconductor industry had became vertically dis-integrated, with separate levels for original equipment manufacturers (OEM) and specialized subsystems manufacturers — yet the mindset of vertical integration typically remained. Today, we’re in an era where the complexity of manufacturing has increased to the point that even the biggest integrated device manufacturers (IDM) like Intel and IBM and TI have to partner to develop technology. With consortia and joint-development projects (JDP) now driving the creation of most new intellectual property (IP) in the industry, and with the increased costs and risks of nanometer-era IC fabrication, we must develop new habits of working together and sharing information. Carrying the theme that “In sharing knowledge we can achieve true enlightenment,” Praxair’s July 17th event at SEMICON West featured keynotes by SEMATECH’s Raj Jammy and processing expert John Borland, discussing the technical challenges of 32nm node transistor fabrication. In the panel discussion that followed (which I had the pleasure of moderating), I attempted to express some “Zen-like” ideas about working together in a harmonious ecosystem. More details from the Praxair panel can be found in SST On the Scene video interviews available online. Meanwhile, DuPont’s July 18th seminar entitled "Technology Partnerships and Tools for the Future" featured presentations by executives from IDMs, OEMs, academia, and a consortium (SEMATECH's Raj Jammy again) on how cooperation is needed to meet the increasingly demanding requirements of advanced ICs. Mansour Moinpour, materials technology and engineering manager for Intel’s global fab materials organization, showed that even the largest company in the industry with potentially the greatest internal resources has used an ever increasing number of partners over the last decade. Large companies today have typically systematized interactions with universities and other research organizations. “I think the challenge is going to be how to make sure that we facilitate the interaction of the small companies with the universities,” explained Farhang Shadman, Regents Professor of Chemical and Environmental Engineering at the U. of Arizona, and director of its Center for Environmentally Benign Semiconductor Manufacturing. “I think this is very important, because they are in greatest need of research facilities.” Basic human trust is essential to making deals that can quickly bear fruit, combined with prior aggregate experience, and some manner of mutual benefit on a strategic level. Jammy said that templates and standards have allowed SEMATECH to reduce the time needed to get a signed contract from one-half year down to weeks. John Behnke, VP of process development and transfer for Spansion, commented, “There are some pretty good templates that the legal community and the different corporations begin with, which helps the process. I think it has matured in the last maybe two to three years. So that helps.” Behnke reminds us that trust is still vital to efficient business, and trust that your ideas will not be stolen is perhaps the most vital. “Let's say that the room is dark and the solution to that is to invent the lightbulb,” he explained. Once the hard work of creating a working lightbulb is complete, “the person who said the room was dark thinks that it's all theirs.” This sort of mindset was not uncommon in the past. Fortunately, it seems that most of us now realize that an attitude of “enlightened altruism”—in which we all work for mutual benefit—really does result in the greatest individual benefit too. –E.K. Labels: ecosystem, fab, IC, partner, semiconductor
posted by [email protected]
070727: Working together to reach nirvana
070525: Intel-IBM fab hype-war and truths
Ed’s Threads 070525 Musings by Ed Korczynski on May 25, 2007
Intel-IBM fab hype-war and truths
It has been said that the first casualty of war is the truth…even more so in a hype-war. An interview appearing on a popular electronics industry Web site is the most recent battlefield in this ongoing hype-war between the world’s semiconductor manufacturing heavyweights. As tradeoffs in fab technology become more fundamental at 45nm nodes and beyond, different companies choose to deploy similar technologies in different ways. The truth is inherently complex and thus a bit complex to describe, and can die under the assault of hype. Among fundamental choices today we find the following: double-patterned dry or single-patterned wet lithography for critical layer patterning, and use of porous or airgap low-k dielectric for on-chip multi-level interconnects. Intel has chosen double-patterned dry lithography and non-airgap low-k dielectrics. IBM has chosen single-patterned wet-lithography and airgap dielectrics. As shown by Hoofman, et.al, in the pages of SST last year, there are many different airgap process flows, which can produce many different airgap structures. Airgaps may be complete or partial between lines, and this is one of the more fundamental parameters to consider in integrating the structures into real chips. Thus, airgap1 is not airgap2 (General Semantics suggests the use of “indexing” to remind us of the essential distinctions between members of any conceptual set). Using “complete airgap” flows and removing all dielectric between lines to achieve the absolute minimum capacitance does indeed create the two general problems articulated by Mark Bohr in the recorded interview: an expensive critical-lithography mask to ensure proper via landings, and copper electromigration sensitivity. However, the IBM flow uses airgaps only in the middle of line spaces while leaving dielectric material on the sidewalls of copper lines. The IBM airgap process exposes parts of some metal sidewalls during the tricky three-stage gap etch, but the subsequent dielectric CVD process re-coats the exposed sidewall areas prior to “pinching off” the tops of gaps. With adequate sidewall dielectric in place, via landing and electromigration issues can be minimized if not avoided. Intel’s Bohr certainly understands airgap integration issues far better than I do, but because he’s not in a position to comment on how his competitor’s process might work, he accurately and properly expressed Intel’s results in the interview, and the generic disadvantages of approaches not currently taken by Intel. However, a statement summarizing the interview reads thusly: “Mark Bohr, Intel senior fellow, says his company looked at air-gap technology like IBM recently introduced, and dismissed it as costly and inefficient.” That's a misinterpretation. The truth is that Intel never panned IBM’s airgap technology—Bohr answered a specific question about IBM’s technology with a generic answer about non-IBM technology. Of course, Bohr can very reasonably say that he has no knowledge if IBM’s technology beyond what is muddied in the official press release. Since IBM’s marketing spun the technology truth to the point of grandiose hype, it provides easy opportunity for Intel to comment on the hype instead of the truth. (Incidentally, further information on the general concept of self-assembled nanotechnology for lithographic masking applications can be found in the most recent issue of Microlithography World.) The IBM hype was that no new lithography is needed. Intel counters that a generic process flow for airgaps requires critical-lithography steps. The truth is that the IBM flow does use an additional lithography step for each airgap level, but it’s non-critical and the mask generation has been automated as a button in the EDA deck. Critical-lithography steps for 45nm node processing can be 10X more expensive than non-critical patterning steps. If the IBM airgap process required critical lithography for each level then it might add 20%-25% to the cost of each chip, but with non-critical lithography it might add only 5%-8%. For most people in the world who lack experience in fab processes, subtle complexities get lost in translation and details are distorted or lost. The truth about nanometer-era fab processes is that they are all tough to develop with inherent integration trade-offs. With Intel and IBM now going down divergent paths, it’s truly difficult to assess a fab technology “leader” in anything but hype. — E.K. Labels: airgap, fab, IBM, IC, Intel, interconnect, low-k, self-assembly, ULK
posted by [email protected]
070525: Intel-IBM fab hype-war and truths
070511: India scripts future for Fab City
Ed’s Threads 070511 Musings by Ed Korczynski on May 11, 2007India scripts future for Fab CityAs I recently wrote in this blog space (see “Turn-key fabs for India”, April 6, 2007), India may soon be joining the world of “fab-ulous” nations. On May 10, “Dr. YSR” Reddy, Chief Minister of the government of Andhra Pradesh (GoAP), and a delegation of IT ministers and advisors were in Silicon Valley to meet the actor governor of California, and also to promote their state as a place for high-tech investment. Andhra Pradesh (AP) claims an information technology (IT) growth rate of 50%-55%, the lowest electricity cost in India, and good water resources. In particular, Hyderabad boasts of a new international airport to be operational by March 2008, an eight-lane outer-ring road and a metro-rail transport system also being built. “With our resources—which are better than many states in the country—we will support the first fabs in India.” said Reddy. “We want to make the infrastructure world-class, and this is being worked out now.” Dr. C.S. Rao, IT advisor for GoAP, provided additional details of the infrastructure priorities. AP has been very successful in pharmaceutical manufacturing, so there is confidence in the same result for semiconductor manufacturing. “GoAP believes strongly that chip manufacturing in AP will generate hundreds of thousands of direct and indirect jobs in AP, and this is one of the reasons it is a very high priority for us,” informed Rao. “These are very exciting times for AP to get in on the ground floor of this opportunity and become a leader in India.” A semiconductor fab requires uninterrupted electricity and water to properly function, and the GoAP understands that supply of these resources will be critical. “GoAP is simultaneously prioritizing the rural sector and the manufacturing sector in AP,” explained Rao. “Therefore the best way to meet these priorities is not sacrifice one for the other but instead have enough supply of water, power, land, etc. so that these priorities can be met simultaneously.”GoAP has issued orders that 10% of water in all irrigation projects in the State should be reserved for industrial uses, but there are many active and developing industries in addition to the Fab city project in Maheswaram in Ranga Reddy. A short list includes: two IT parks, one IT Special Economic Zone (SEZ), one hardware SEZ, one IT industrial park, and a gems and jewelry park. Despite conflicting requirements for basic resources, the government seems to have set proper priorities to establish semiconductor fabs. GoAP has already committed to installing by the end of this year a pipeline capable of carrying dedicated capacity of 20 million gallons of water/day for multiple fabs and other manufacturing in Fab City. "This pipeline is already started to be laid out and will be done,” said Rao. “There is no conflict here.” Regarding the electric power, up to 200 MW of power is being made available for Fab City with two different grid lines. “Again, the commitment by the government of Andhra Pradesh is total and comprehensive,” said Rao, noting that the government of AP will be minor partners in projects spanning the 1200 acres of Fab City. Though 200 MW is a great amount of power, it will be easily consumed by a handful of fabs and supporting businesses. A typical 200mm fab with 20,000 wafer starts/month (WSPM) fab consumes ~130 kWh/yr of electricity, according to a World Wide Fab Energy Survey Report published by International SEMATECH (Technology Transfer # 99023669B-ENG, June 30, 1999). Assuming steady consumption, average 200mm fabs thus need ~17 MW of electricity to run. Applying the 1.5x rule for 300mm tool scaling, most 300mm fabs would consume (1.5 x 17) ~25 MW for 20,000 WSPM; however, since most 300mm fabs are scaled to >30,000 WSPM their typical power needs scale proportionally to >38 MW continuous power. It looks like the first commercial chip-making facility in FabCity will be a SEMindia test and assembly line (i.e., “die-based final manufacturing”) supposedly breaking ground within weeks. Test and assembly lines typically don’t consume nearly as much power and water as IC fabs (i.e., “wafer-based manufacturing”) and they are really quite different manufacturing environments, though still part of the “chip-making ecosystem.” SEMindia still plans to eventually startup an IC fab in Fab City, but a start date is currently tentative since partner AMD has slowed capex spending. The first IC fab in Fab City is supposedly again going to be that of Nano-Tech Silicon India Ltd. (NTSI), a start-up led by South Korean businessman/technologist Dr. Jun Min. NTSI has been trying to close financing for at least two years, and though the company had at one point claimed Intel Capital was an investor, as of today no official relationship seems to exist between the two. Rao told WaferNEWS that Min is “doubly confidant that he will be able to have financial closures with prospective investors in the next 90 days” -- but the basic structure of the project has been scaled down, with phase1 capacity plan reduced from 30,000 WSPM to 20,000 WSPM. An entire used 200mm tool set can be acquired for <$50 million these days, so maybe the NTSI project will now finally move forward. Many details remain to be resolved with specific projects, but at least the government seems to have a clear policy of support for fabs, and it now seems to be a race to first silicon. Will NTSI get its financing together in time? Will HSMC and Infineon get its turn-key fab up and running first? Will SEMindia and AMD find money for a fab? One way or the other, it now looks like Fab City in Hyderabad in Andhra Pradesh should be producing ICs on silicon wafers within two years. —E.K. Labels: fab, Fab City, HSMC, Hyderabad, India, NTSI, SEMindia
posted by [email protected]
070511: India scripts future for Fab City
070504: IBM add airgaps for faster chips
Ed’s Threads 070504 Musings by Ed Korczynski on May 04, 2007 (updated June 12, 2007 to correct details of the IBM airgap etch process, which had erroneously referred to the third-step being RIE, when it is wet as confirmed by both D. Edelstein and S. Nitta)IBM adds airgaps for faster chips
Airgaps have long been considered as structures to increase the speed of on-chip IC interconnects, though no one had developed manufacturing-worthy process flows. Only in the last year have companies such as Philips (now NXP) shown overviews of likely airgap manufacturing processes, though without production commitments. Now IBM has invented a new variation on airgaps that uses a self-assembling polymer mask layer as part of the process flow, and claims this can be a simple drop-in addition that adds only ~1% to chip cost for each dielectric layer gapped. Thus for an advanced multilevel interconnect, a ~5% cost adder should provide 35% faster chips or 15% less power consumption. Circuit speeds are limited by the dielectric constant (k) of the insulating material surrounding metal lines, so the industry's Roadmap has focused on ever lower k dielectric materials. Unfortunately, materials engineering for a new dielectric material is difficult and expensive, and despite tremendous efforts and many false-starts over the years, the entire world has now settled on SiCOH by CVD as the lone dielectric material (k~3) that provides acceptable cost, yield, and reliability. So-called ultralow-k (ULK, aka “extreme low-k”) films are merely k~3 SiCOH with the addition of ~20%-40% by volume of nanopores to reach k~2.4. More nanopores cannot be added without degrading yield and reliability, so the only practical way to get to k~2 is to incorporate a single large pore with clever processing as an “airgap.” A multiyear development effort to create a manufacturable airgap process was led by IBM fellow Dan Edelstein, program manager for low-k CVD BEOL, who provided Solid State Technology and WaferNews with exclusive insight into how they achieved these remarkable results. He explained that unlike previously known airgap process flows, the IBM approach starts with a standard dual-damascene copper and SiCOH dielectric process that has been in production for years. Airgaps are formed using a multi-step etch, using a hardmask patterned with either self-assembling monolayers or standard lithography depending upon the geometry of the interconnect. Unfortunately, IBM's press release touting the airgap achievement is so grossly hyped that it’s caused severe misunderstanding throughout most press reports on this process. The new technique "skips the masking and light-etching process,” says the official release. “Instead IBM scientists discovered the right mix of compounds, which they pour onto a silicon wafer with the wired chip patterns, then bake it.” In reality, while self-assembly can be used to make an array of nominally 20nm holes by spin-coating and baking, these holes merely pattern the hardmask that is used to etch the gaps into the dielectric, explained Edelstein. A non-critical lithography step is used to block out circuit areas that do not need gaps, he said. The self-assembly layer is not even used to pattern the hardmask used to make airgaps at upper levels of the interconnect. “At some point in the hierarchy it becomes more viable to use lithography instead of self-assembly,” he said. While IBM doesn't use airgaps for the first level of metal, they could be used at any of the higher levels within the hierarchical interconnect stack, Edelstein noted. “Most chips won’t need air-gaps on all levels, but perhaps on half,” he said. No matter the level, a special three-step etch process to form gaps with narrow top openings is the key to this process (see figure). “We etch a narrow channel down so it will cap off, then deliberately damage the dielectric and etch it so it looks like a balloon,” he explained. “You have a big gap with a drop in capacitance and then a small slot that gets pinched off.” Starting with dual-damascene copper lines/vias and SiCOH single-phase dielectric, the essential IBM airgap process flow is as follows: 1) Deposit hardmask; 2) Spin-coat an imaging layer; either special new diblock polymer or standard photoresist; 3) Create holes using either the self-assembly properties of the diblock or standard lithography; 4) Block out circuit areas to not be etched using non-critical photolithography; 5) Transfer holes from the imaging layer to the hardmask; 6) Etch three-step sequence—first an anisotropic RIE to form deep openings into SiCOH, then plasma damage of the column sidewalls, then isotropic wet etch to remove most of the remaining SiCOH underneath the hardmask; 7) Strip hardmask; and 8) PECVD of the next SiCOH dielectric level to cap the gaps with a classic “pinch-off” shape. Since the self-assembling mask layer is not aligned to the underlying interconnect structures, and since the block-out mask is “non-critical” to save costs, the hardmask will inevitably expose the tops and sides of some metal lines to RIE. Consequently, the SiCOH etch chemistry needs to have excellent selectivity so as to not attack copper and any metallic barrier layers. Edelstein says that they’ve been able to work with standard gas precursors for this critical RIE step. The new airgap process is an optional loop off of the standard flow, so designers can choose to use airgaps at any of the levels in the on-chip interconnect hierarchy—and IBM also has developed an automated algorithm for making the block-out mask. “As a customer you can turn on the air-gap option for any level on any chip. We can put the gaps in independent of any incoming design,” Edelstein told WaferNEWS. The ability to add air-gaps as a “drop-in” to an existing on-chip interconnect process flow minimizes risks, and explains the company’s confidence that this flow will be used in manufacturing by 2009. While the diblock polymer is only one part of this airgap process, it is a significant addition. Chemists at IBM Almaden Research reportedly developed this material for broad applications in fabs—it’s like a standard photoresist in terms of handling and dispensing, it has a wide process window, and IBM has detected no shelf-life problems for up to one year. Using self-assembly in coordination with lithography opens up new possibilities in general for integrated process flows, so look for news of additional applications in coming years. “We hope that we can use directed self-assembly to get to other device features,” said Edelstein. “This is just the tip of the iceberg.” — E.K. Labels: airgap, fab, IBM, IC, interconnect, low-k, self-assebly, ULK
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070504: IBM add airgaps for faster chips
070427: Life after CMOS commoditization
Ed’s Threads 070427 Musings by Ed Korczynski on April 27, 2007Planning for life after CMOS commoditization...todayIt’s hard to feel upbeat about the future of mainstream semiconductor manufacturing after attending this year’s SEMI Strategic Business Conference in Napa, CA, where presentations detailed the end of the good times. After decades of leading the world in high-tech value-adding, the IC business is now mature and just another part of the global electronics industry. This is nice enough, unless you remember the record revenues, profits, and capital equipment expenditure levels of the 1990s. Trends within the IC industry indicate that the average cost to develop a new IC product has risen from $10M at the 90nm node to $50M at 65nm. With a targeted 10x return on research and devleopment over the life of the product, you need to see over $500M in chip sales for a single 65nm product. Remembering that consumer chips typically sell for $5 each in quantity, that means before even starting a new 65nm chip design you need to show demand for 100M units, which will effectively lock out a number of applications spaces, noted Wil Josquin, VP of strategy and innovation for NXP Semiconductors. In his concluding keynote presentation, Art Zafiropoulo, CEO of Ultratech, included a slide from Freescale showing the percent of investment into a final IC product going toward packaging has gone from <20%>50% in the last five years. His final slide ended with the final line reading that advanced packaging will be the only differentiating technology. Amkor’s David Hays, VP of business development, wafer level processing, reminded the audience that, “There’s no way to get all the features and functions in cell phones that we all want using old chips and old packages.” For example, Motorola’s trend-setting V3 RaZR handset includes six chip-scale packages (CSP) plus 14 wafer-level packages (WLP). Despite providing substantial value, outsourced semiconductor assembly and test (OSAT) providers such as Amkor or STATS/ChipPac find it difficult to make a profit. “The industry doesn’t want to pay us to do the work we do,” Hays lamented. “It’s like Walmart -- they’ll say what they’re willing to pay for it, and it’s up to you to figure out a way to make a profit.” There are seemingly no more obvious and easy solutions available. If you do a silicon chip shrink from 90nm to 65nm nodes for cost savings, you may find that the added packaging cost to handle a smaller chip with tighter pitches negates any saving in the silicon. Consumerization drives rapid electronic product life cycles that stress the supply chain. Scott DeBoer, Micron’s director of process development, reminds us that commodity pricing can be very volatile —e.g., NAND flash spot prices averaged $9.50 on Dec. 1, but had sunk to $5.15 by Jan. 26. Extremely tight coordination is required between EDA, IP, fab, packaging, and ATE partners to have any hope of first silicon right. Plus, after decades of evolution, nanometer-scale CMOS logic technology has reached commoditization, such that the chip itself just doesn’t make the product any longer. Future added-value will come from software and advanced packages and bundled-internet-subscriber-services, not from the ICs which power it all. With Intel sending 90nm logic technology to China, and TI stopping CMOS development at 45nm, the writing is clearly on the wall. Mike Thompson, manufacturing operations GM for STMicroelectronics, did the math for why TI said no more, concluding that process technology spending as a % of development is being squeezed out by increasing efforts in software development for new products in the ASIC/ASSP world. With ~$400M required to develop a new silicon process technology, if this is 20% of the total research and development budget which is capped at 20% of total sales, then only IDMs with >$10B IC revenue can maintain independence in silicon process technology development. For logic technology, the world is settling down to just three or four independent sources of mainstream CMOS technology development: Intel, the IBM ecosystem, the foundries, and Japan. IBM continues to lead the industry in technology innovation as the center of the collection of partners in the Common Platform Alliance (CPA). This alliance includes many design and packaging members who add value beyond the limits of silicon, such as Amkor, ARM, Analog Bits, Blaze, Chipidea, Clear Shape, Cadence, Magma, Mentor Graphics, Ponte, Synopsys, and Virage Logic. The industry continues to innovate using current business models, though we should expect to see many shake ups below the first-tier of IDMs, OEMs, and OSATs. Major IDMs will continue to manufacture in-house, though they will both provide and use more and more foundry services. Fabless companies will continue to function as they have in recent years, with clear distinctions between the top-tier and all others. Medium-size IDMs will partner to remain “fast-followers.” If you’re supplying equipment or materials to leading-edge fabs, expect that greater purchasing power will consolidate into fewer hands. Overall what can we expect from the new reality of CMOS logic commoditization? Keep up the good work, and you might even get paid some day. — E.K. Labels: business, CMOS, commodity, fab, IC, strategy
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070427: Life after CMOS commoditization
070406: Turn-key fabs for India
Ed’s Threads 070406 Musings by Ed Korczynski on April 06, 2007Turn-key fabs for IndiaThe tide has turned, and it looks like India will finally be joining the club of fab-ed nations. Hindustan Semiconductor Manufacturing Corp. (HSMC) has partnered with Infineon to build at least two fabs in Hyerdabad, with first silicon planned for 2009. The first 200mm fab will run 130nm CMOS processes and cost ~$1 billion, and the second 300mm fab will cost US$3.2-$3.5 billion. Infineon will also license its design libraries for ICs targeting mobile phones, ID cards, and automotives. Infineon touts its record of going from cornerstone of the fab to first-wafer-out in under one year in Malaysia, so it has set a clear precedent for successful greenfield fabs in previously undeveloped regions. However, with several other previously proposed Indian fabs abandoned, many analysts currently doubt the likelihood of success of HSMC. TI recently said no to building a fab in India, and Intel, though courted by India, chose China for a new 90nm logic fab. Many analysts site “infrastructure” issues as the primary obstacles for fabs in India, contrasted to Intel’s choice of China as a more viable region today. In comparing India to China in this regard, I take a longer term perspective and see that India may be today where China was just 10 years ago. When the PRC started Project 909 in 1997 as part of their 9th five-year-plan, it was the first 200mm submicron fab in the country, and many people questioned whether it could succeed given the perceived problems with the infrastructure. In particular, Shanghai has had electrical power supply problems with black-outs and brown-outs common for the last decade as it grew factories at a frantic pace. Yet the government understood that power loss to a fab causes greater problems than simple downtime, and it set the priority that semiconductor fabs will always get power. All you really need to keep a fab running is a road to an international airport, water, electricity, and mostly clean air (and the outside air has to be seriously bad to make a difference—i.e., the 1997 massive forest fires in Indonesia that messed up fabs in Singapore). If a government is motivated to set priorities, then it can all be established in a year or two. For example, the original Motorola MOS-17 fab, now owned and operated by SMIC, was built in Tianjin, China, which is separated from the international airport in Beijing by a mountain pass regularly closed by snowfall in the winter. With priority snowplows, the road closes for at most one or two days to keep supplies running. Similarly, water can be prioritized, and newer fabs can be run with more efficient reduce/reuse/recycle strategies to minimize consumption. The competition between industry, agriculture, and people for water rights remains a very politically sensitive issue, but if there’s the will there’s the way. Incidentally, the very ground upon which the fab is built doesn’t even have to be that stable. SMIC and GSMC had to spend an extra few months and rumored hundreds of million of dollars to drive special “resistance” foundation pylons more than 100 feet deep into the marshy land of PuDong (similar to the building of the world-famous and still productive Ford Motor Company Rouge Plant over 2000 acres of “bottomland” in Dearborn, Michigan). SEMindia has lobbied the government to provide the infrastructure needed. Hyderabad is building a new international airport—not coincidentally near Fab City, along with freeways, new power-generation, and water has been set aside. So it all seems rather do-able—if Indian leaders make it a priority. Unfortunately, a prominent politician has reportedly dampened some fab plans by insisting that there is limited room in Hyerdabad for only 3-4 fabs instead of the 10 ultimately proposed by HSMC. It is difficult to interpret this as encouraging, though it may reflect the government’s reasonable assessment of the near-term limits to how much they can stretch the infrastructure. There are already two other fabs in the works. SEMindia partnered with AMD to build a wafer fab that is still planned, while they have already started on a scaled down $250 million assembly and test plant. Nano-Tech Silicon India (NTSI)—a fab set up with used 200mm tools and led by a South Korean businessman—is supposed to see first silicon out this year. SiliconIndia is a network of “non-resident Indian” (NRI) talent that may return to help launch fabs. Let’s see what happens, but I predict ultimate success for Fab City and semiconductor manufacturing in India. — E.K. Labels: fab, Fab City, HSMC, Hyerdabad, India, NTSI, SEMindia
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070406: Turn-key fabs for India
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