Ed’s Threads 080613
The last musings in this blog on Friday the 13th of June, 2008

Process integration drives the IC industry
The next 10 years will witness more changes in mainstream manufacturing technology for ICs than in the last 40 years combined. An industry based on “what have you done for me lately” can never rest on its laurels, and so innovation must continue, despite limits in 2D scaling. With rapidly escalating costs projected for 32nm node and smaller digital CMOS manufacturing, it is inevitable that IC companies look to analog, packaging, and heterogeneous integration to add relatively greater value for lower cost and risk. Unique process integration challenges at each fab will drive everything for the next ten years, as shown recently by presentations at the recent International Interconnect Technology Conference IITC., some of which I've already discussed in this blog.

What are the ramifications of all of these subtle changes? With basic “unit-process” building blocks fairly well established, it is likely that the only fundamentally new tools to be developed will be for metrology. The current generation of thin-film, lithography, and thermal processing tools are extremely productive and should continue to be used with modest evolutionary upgrades over the next 10 years. The only exception to this is probably EUV lithography, which is still under development but shows promise.

New integration of old processes can be seen in the evolution of barrier layers for Cu metal in dual-damascene structures. At IITC, Novellus showed that PVD Ti/TiN is the newest Cu barrier to replace Ta -- though Ti is the standard barrier for Al metal lines it was replaced by Ta when the industry first began using Cu lines. Though less expensive than Ta, Ti can react with both fluorine (in FSG dielectric) and Cu and so was not considered to be an acceptable barrier. However, now that FSG has been replaced with SiOC in many fabs, a 5nm thin TiN layer (formed with 50 at% N) capping on Ti stops Cu diffusion. An ultra-thin PVD Ti wetting layer on top of the TiN provides a good surface for ECD fill of Cu.

NEC has targeted high-reliability automobile MCUs, and examined PVD Ti/Ru barrier metal for these applications. After 7 hours at 350°C, Ti diffuses into the Ru, but no Cu diffuses through the Ti. PVD-Ru with (001) orientation can be removed by CMP using conventional slurry for Ta/TaN removal. The Ru barrier achieved 12% lower resistance than the conventional Ta type barrier for 70nm wide Cu lines, while time-dependent dielectric breakdown (TDDB) was unchanged. The Ru/Ti barrier shows 35× longer lifetime (T50) than Ta/TaN. Whatever process is finally developed will run for over 10 years with essentially no changes, as per the supply contracts to the auto industry. I toured NEC Roseville recently and saw old 200mm tools being installed with plans to run for >10 years using ≥150nm node processes.

Low-k air-gaps are also great examples of using old unit-processes in new ways, since CVD oxides (SiOx and SiOC) and spin-on polymers already well developed will be used, while established lithography and etching technologies will complete the integration. EDN's Ron Wilson covered many of the latest air-gap integration details from IITC in his fine blog, but the most important consideration is that no new manufacturing tools are needed to make them happen. Designs may need to be tweaked, and the process integration will be challenging, but this approach is relatively low-risk and may be integrated into older fab lines.

Further proving that “there is no more noise (…there is only signal),” IMEC’s Michele Stucchi at IITC examined the effects of inherent line-edge roughness (LER) and via misalignments on the Efield and electrical breakdown between wires. An enhanced electrical field between adjacent lines is induced by LER-induced reduction in spacing. Compared to a nominal electrical field between lines with zero LER, a probabilistic analysis results in enhancement to the field, which can be a factor >2 in 30nm spaced lines. For wires with 30nm spacing, Efield may be high enough to guarantee at least one bridge in 20μm of line length. For via misalignment of 10nm in standard dual-damascene structures with 30nm spacing, the field enhancement can be a factor >3.

An amazing example of tricky process integration to eliminate variability in lithography was shown by Matthew Breitwisch of IBM, in describing work with Macronyx on phase-change memory (PCM) technology. Ge2Sb2Te5 (GST) was the first material investigated which changes from a high-resistance amorphous structure to a low-resistance crystal at ~170°C. A PCM cell is made up of a variable resistor in series with an access device (which may be a diode, BJT, or FET), and current flux near one million A/cm2 is needed for a few nanoseconds to create the change. To concentrate the current in programming, uniform small pores are achieved using a key-hole (a.k.a., “pinch-off CVD”) process:

- blanket oxide, hardmask and nitride depositions,
- lithography,
- anisotropic etching through the dielectric stack,
- an isotropic oxide etch to create an undercut below the hardmask, and
- conformal polysilicon CVD to form consistent 43nm wide keyholes.

The keyhole widths are controlled by the oxide etch and the poly CVD, and not by the lithography, such that equally sized pores form in the middle of line spaces of varying width…all without any new unit-processes.

With razor-thin process windows and systematic process-design interactions, each fab may have to optimize its own integrated process flow. If each fab runs a unique flow, then a mask-set run on one line will yield very differently on a second line, and this reality may create problems for companies trying dual-sourcing with foundries.

New materials and evolutionary upgrades to old materials will continue to support new integration schemes in fabs, while most of the tools will remain the same. However, OEM applications labs will run non-stop as fabs try new designs-of-experiments (DOE) for new integration schemes. It will be increasingly difficult to get process information out of fabs, since each line will have to be set up with unique tricks and integration schemes. Designers will have to really start innovating, as digital CMOS shrinks no longer guarantee lower cost and higher performance.

There will be many IC types that will probably never be designed at the 32nm node. A friend working on a graphics processing chip explained to me that they needed to go to 65nm to get a speed improvement for their target application, but their modeling shows that additional speed will now provide no user benefit. Going to 45nm adds huge design costs and manufacturing yield risk, and so they now plan to stick to 65nm but work on cost and power optimization in re-design. Their next 65nm chip may use 3D interconnects or integrated passives for improved performance, however, so innovation will continue… just in new directions. Such is the blessing/curse of “living in interesting times.”

Henceforth, my challenges will be elsewhere. This is my last blog post on my last day as a Technical Editor for Solid State Technology magazine; I am resigning to pursue other interests, first of which will be an immediate 8-week sabbatical. When I return, I will probably work for the semiconductor manufacturing industry, in an as-yet undetermined capacity that doubtlessly will be "interesting." I thank PennWell Publishing for years of rewarding employment, and wish the company well. Special thanks to James Montgomery, who diligently and masterfully copy edited most of these 76 postings.

—E.K.

Labels: 32nm, 3D, airgap, CMOS, copper, IITC, integration, interconnect, process, research

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080613: Process integration drives the IC industry

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Ed’s Threads 080211
Musings by Ed Korczynski on February 11, 2008

IITC process units and integration
The International Interconnect Technology Conference (IITC) has issued its 11th call for papers, and for a change it will explicitly focus on unit processes (and new materials) while continuing to cover the leading edge of integration. The main deadline for paper submissions has now passed, but a limited number of late papers will be accepted until April 11th. The shift in emphasis toward covering unit processes is due to the divergence of integration options moving forward.

Manufacturing ICs on silicon wafers is very complex; hundreds of “unit process” steps (e.g., clean, inspection, etch, deposition, etc) are combined into dozens of “integrated process modules” to form functional structures. One integrated process module may form high-performance transistors, another module forms contacts to transistors, and yet another module forms interconnects between contacts. Many of the unit process steps are copied between modules, and thus has it been since the 1960s.

During the last twenty years, the digital CMOS shrink has been the one process integration direction uniting all the different unit processes under development. The set of requirements for the next node/generation of digital CMOS was always the most challenging for equipment manufacturers working on unit processes. However, starting with the 45nm node, the integration of unit processes has become so complex that there is no one obvious solution for all fabs.

Dr. Thomas Caulfield, EVP of sales, marketing, and customer service for Novellus Systems and former technology executive with IBM, talked with WaferNEWS about the changes in the development of unit-processes in the industry. “As an industry becomes commoditized, how to you differentiate? You either have more efficient design, or more efficient unit processes that allow you to get more productivity or functionality out of the manufacturing. So the last thing you want is the same integrated process,” explained Caulfield. With the leading-edge of IC manufacturing ever increasing in complexity, the productivity of tools used in the fab must increase just to keep costs the same.

Consider the process module to form contacts as an example of integration. Today, the formation of advanced contacts requires something like the following sequence of unit processes:

1) CVD of a blanket dielectric layer,
2) Thermal treatment to stabilize/planarize,
3) Metrology to inspect the layer,
4) Photoresist mask spin-on and bake,
5) Lithography to form initial openings,
6) Treatment to shrink the opening,
7) Metrology to inspect the photoresist,
8) Etch of the dielectric through the mask,
9) Strip/Ash the remaining photoresist,
10) Clean/Treat the dielectric openings,
11) Metrology to inspect openings,
12) Deposit metal barrier layer,
13) Deposit metal for contact,
14) CMP of metal layers, and
15) Metrology to inspect contacts.

Each of these steps has sub-steps too.

In the past, major developments could be described and documented at the integrated process module level, allowing much of the unit process details to be IP secrets. The amazing innovation that enabled digital CMOS shrinks is now pushing against limits of atoms and wavelengths of light, and it now seems clear that further pushes will be ever more expensive. Fabs will also work to integrate analog, RF circuitry, integrated passives, and 3D packages using essentially the same unit processes. “It’s no longer Moore’s Law one-size-fits-all with all the focus on the next generation technology,” explained Caulfield.

Since the integrated process details are now quite sensitive, technologists are relatively more able to talk about developments in unit processes. From an equipment supplier perspective, of course, unit process development does not occur in isolation. “You develop a process capability because you have an application and market in mind,” explains Caulfield. “It’s not that we don’t keep doing that, but today we find customers using the same unit processes in novel ways.”

EDN’s Ron Wilson recently blogged about the IITC call-for-papers and the ramifications of unit process development for IC designers. He considers that porting a physical design from one fab to another may soon require significant inputs from equipment manufacturers, but it is highly unlikely that designers will ever have to talk to OEMs about GDSII files. Using the example of the contact module, the variations in the geometry of the metal contact plug are due to the interdependencies between the different unit processes. Sometimes the source of a structural variation can be easily identified as one unit process, but more often it is impossible to separate out which of the unit processes were to blame. If the diameter of the contact is too large, was the resist overexposed, or was the dielectric overetched?

In addition to the complexity that can be seen in final device structures on the atomic-scale, there are many sacrificial thin-film layers and other “hidden” unit processes within the integrated flow. “It’s funny to watch people debate how something was done based on the data from reverse engineering a final chip,” commented Caulfield. “There’s just no way to conclusively determine the process sequence afterwards with so many sacrificial steps in the integration scheme.”

For example, Novellus sells a pseudo-ALD dielectric tool that forms what they call a pulsed-deposition layer (PDL). Some DRAM fabs use a sacrificial dielectric which they remove with a wet etch, and for this integration scheme the PDL provides no advantage. However, other DRAM fabs use CMP to remove the equivalent sacrificial dielectric, and for them the PDL provides an advantage. The reasons for choosing one integration approach over another are very complex. “People are leveraging unit processes in different ways to try to get the best results while going to higher density,” explained Caulfield. “Productivity or manufacturability differentiation through proprietary integration schemes is the goal—and there are many ways to skin the cat—that provides competitive advantage.”

OEMs have always sold tools that perform basic unit processes, and fabs have always fine-tuned unit processes for integration into modules. The only fundamental change now is that fabs must manage extreme complexity at the same time that most chips have become commodities. “It’s a big problem that the industry is adding manufacturing complexity at the same time that chips are becoming commoditized,” expressed Caulfield. “If you’re not on a curve to take cost out of running a manufacturing tool, then you’ll become the problem that gets worked out of the equation next.”

—E.K.

Labels: CMOS, IITC, integration, OEM, PDL, process, unit

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080211: IITC process units and integration

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Ed’s Threads 070824
Musings by Ed Korczynski on August 24, 2007

Intel finds signs of heterogeneous life after silicon
With CMOS circuits using silicon channels running into performance limitations, doping with germanium and straining the lattice have already been used to push the limits. The limits of silicon remain, though, and so compound semiconductors are again under consideration as building blocks for mainstream ICs—this time integrated on top of 300mm silicon wafers.

The first solid-state transistors were built with germanium (Ge), but Ge crystals do not grow a nice surface-passivating oxide as do silicon crystals, and the oxide is vital to prevent surface defects that would otherwise kill performance. Grown silicon oxide has been the heart of cost-effective high-volume IC production for over 40 years. Even high-k (HK) gate dielectrics based on hafnium-oxides will typically be used on top of a grown and partially etched-back silicon oxide layer.

What comes after high-k and metal-gates (HK+MG)? Heterogeneous integration of compound semiconductors will completely replace the silicon channel. Silicon wafers would still be used, but only as physical supports for different NMOS and PMOS transistor materials. The new channel materials will be deposited and/or grown using technologies such as metal-organic CVD (MOCVD), solid-phase epitaxy (SPE), and spike/flash anneals.

Though HK+MG has been spun as the biggest change in 40 years, when compound semiconductors are integrated with silicon it will be a far greater integration challenge for it will require an even greater number of new materials. Now Intel researchers have reported passing a milestone along the road many travel to heterogeneous integration: integrated superior device performance.

This summer, Intel researchers achieved success at fabricating high performance devices using both indium antimony (InSb) and indium gallium arsenide (InGaAs) channels, and in each case they perform as well as their counterparts on GaAs wafers. On their internal blog, they show curves for the performance of both types of devices, with individual transistors both higher performing and consuming less power than equivalently sized silicon devices.

Mike Mayberry, Intel’s director of components research, has articulated five general areas of research and develop needed to create a competitive commercial heterogeneous semiconductor fab technology:
1) put compound semiconductors on silicon wafers,
2) find different high-k dielectrics for the gates,
3) develop PMOS materials to go with known NMOS,
4) develop enhancement-mode devices instead of depletion-mode, and
5) “Make them small enough to compete with silicon transistor densities.”

The last is the tricky part. These circuits are conceived of as being possible at or past the 22nm node, so that means high-yielding dense 32nm and likely 22nm CMOS circuits will already be in production using strained SiGe. Heterogeneous circuits will have to compete with Si/SiGe chips on price, so transistor packing density will be crucial.

By the time InSb and InGaAs could be integrated on silicon wafers, finFETs should also be options along with planar transistor structures. In an email exchange with me after his initial blog posting, Mayberry answered some questions relating to finFETs as possible structures for heterogeneous integration. “It is possible that in the timeframe we’re discussing that trigate structures could be a strong candidate and thus, that builds pressure to find a vertical solution for III-V,” he confirmed, but he admitted that, “we do not as yet have a solution to that problem.”

If finFETs are used, new metal alloys will need to be developed to be able to form minimal resistance electrical contacts to these new materials. Even if planar structures are used, the contacts will almost certainly be to the channel material instead of silicon to avoid the need for a >5nm transition zone from material to material that would otherwise limit packing density. Due to the need for this transition layer in planar devices with silicon contacts, and the performance advantages to a reduced number of boundary layers, it seems likely that metal contacts will be direct to the new compound semiconductor materials.

In my email exchange with Mayberry, he confirmed only that “we have not decided how to make electrical contact for those future devices.” One thing he knows—and will let us know—is that for Intel’s current work, SOI would just get in the way and everything is grown on bulk silicon wafers.

This is all starting to get into some serious materials engineering. Mayberry’s blog pre-announces that they will show enhancement-mode device results using these materials at IEDM this December. Since these newest devices will be “normally off” they should result in minimal leakage and reduced power-consumption for circuits. We can almost certainly expect unexpected subtle second-order integration challenges with all of these new materials, with the semiconductor industry now moving into “interesting times.”

–E.K.

Labels: compound semiconductor, heterogeneous, IC, integration, Intel

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070824: Intel finds signs of heterogeneous life after silicon

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Ed’s Threads 070323
Musings by Ed Korczynski on March 23, 2007

Integration extends 193nm litho
As thoroughly reported by WaferNews, SST, and Microlithography World, the 2007 SPIE lithography meeting detailed that 193nm wavelength lithographic reduction steppers may be the last mainstream lithographic technology for the semiconductor manufacturing industry. Whether dry or with the wafer under immersion (193i) of a fluid to push the resolution, there really is no other choice besides direct-write. Consequently, process development engineers now look for ways to create ever smaller device features using 193nm litho with clever combinations of other known unit-process steps: thin-film depositions, etches, and plasma surface treatments.

Double-exposure (in which a single resist stack is exposed twice) and double-patterning (with at least one thin-film hard mask, and usually two exposures) with 193nm are now in use and under development in different CMOS fabs. Double- and triple-patterning has been used in the MEMS industry for over 20 years, to allow for all lithography to be completed before complex multi-step etching of physical structures such as membranes and cantilevers.

A classic and well-known integration trick to extend litho is “resist-trim.” Used for gate formation, resist lines defined by lithography are plasma etched to thin them and so achieve linewidths below the resolution of the optics. Various resist-swelling techniques can narrow contact holes below lithographic resolution limits. Applied Materials now claims an anisotropic plasma etch of a hardmask can narrow holes.

Applied Materials now also touts two different hardmask materials: a dielectric advanced patterning film (APF) for most applications, and a 25-30nm thick PVD titanium nitride (TiN) film for integration with low-k dielectrics having porosity of up to 30%. The $2-$3/wafer APF has the amazing ability to “heal” line-edge roughness (LER) from an upper resist layer. Because it is not built out of large molecules like resist, the byproducts of etching the APF are small ligands with sp3 hybrid bonds that coat exposed sidewalls with diamond-like carbon, which preferentially fills in 1-2nm features. Consequently, LER of 2.5 nm in resist becomes just 1.5 nm when etched into the APF.

Applied Materials has developed a complex, self-aligned double-patterning scheme that uses a quadruple-hardmask and a self-aligned spacer nitride with a single litho step:
- Depositing a blanket stack of APF + oxide + APF + nitride on top of poly,
- Coat resist and dry 193nm litho of pattern into resist,
- Trim resist, then etch pattern into nitride and top APF,
- Deposit self-aligned sidewall spacer nitride,
- Etch APF, and then
- Etch poly gate features using remaining spacer nitride.

Improved metrology will certainly be essential to manage any of this new integration. Metrology now controls the process—it doesn’t merely monitor—and it must also provide the vital data to build design and litho models. For example, building an OPC model requires accurate metrology to capture the interdependencies between the mask, resist, and at least one etch. Thus, SPIE now includes thorough sessions on DFM and metrology.

The history of semiconductor manufacturing technology is the history of risk-avoidance at the bleeding-edge of human knowledge. “The industry is overall conservative as any manufacturing industry must be,” commented TI’s Hans Stork in his keynote address at SPIE this year. “We only move to a new material or a new approach if there is no alternative.”

Technologies must hit the sweet spot in the middle of capability/risk/cost, and it’s the overall integrated process that counts. If multiple low-risk and inexpensive process steps can replace a single risky and overall more expensive step, then the reduced cost and risk of the multi-step flow will always be worth the longer fab cycle-time.

—E.K.

Labels: 193, direct write, hardmask, integration, LER, litho

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070323: Integration extends 193nm litho

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