Ed’s Threads 080613
The last musings in this blog on Friday the 13th of June, 2008

Process integration drives the IC industry
The next 10 years will witness more changes in mainstream manufacturing technology for ICs than in the last 40 years combined. An industry based on “what have you done for me lately” can never rest on its laurels, and so innovation must continue, despite limits in 2D scaling. With rapidly escalating costs projected for 32nm node and smaller digital CMOS manufacturing, it is inevitable that IC companies look to analog, packaging, and heterogeneous integration to add relatively greater value for lower cost and risk. Unique process integration challenges at each fab will drive everything for the next ten years, as shown recently by presentations at the recent International Interconnect Technology Conference IITC., some of which I've already discussed in this blog.

What are the ramifications of all of these subtle changes? With basic “unit-process” building blocks fairly well established, it is likely that the only fundamentally new tools to be developed will be for metrology. The current generation of thin-film, lithography, and thermal processing tools are extremely productive and should continue to be used with modest evolutionary upgrades over the next 10 years. The only exception to this is probably EUV lithography, which is still under development but shows promise.

New integration of old processes can be seen in the evolution of barrier layers for Cu metal in dual-damascene structures. At IITC, Novellus showed that PVD Ti/TiN is the newest Cu barrier to replace Ta -- though Ti is the standard barrier for Al metal lines it was replaced by Ta when the industry first began using Cu lines. Though less expensive than Ta, Ti can react with both fluorine (in FSG dielectric) and Cu and so was not considered to be an acceptable barrier. However, now that FSG has been replaced with SiOC in many fabs, a 5nm thin TiN layer (formed with 50 at% N) capping on Ti stops Cu diffusion. An ultra-thin PVD Ti wetting layer on top of the TiN provides a good surface for ECD fill of Cu.

NEC has targeted high-reliability automobile MCUs, and examined PVD Ti/Ru barrier metal for these applications. After 7 hours at 350°C, Ti diffuses into the Ru, but no Cu diffuses through the Ti. PVD-Ru with (001) orientation can be removed by CMP using conventional slurry for Ta/TaN removal. The Ru barrier achieved 12% lower resistance than the conventional Ta type barrier for 70nm wide Cu lines, while time-dependent dielectric breakdown (TDDB) was unchanged. The Ru/Ti barrier shows 35× longer lifetime (T50) than Ta/TaN. Whatever process is finally developed will run for over 10 years with essentially no changes, as per the supply contracts to the auto industry. I toured NEC Roseville recently and saw old 200mm tools being installed with plans to run for >10 years using ≥150nm node processes.

Low-k air-gaps are also great examples of using old unit-processes in new ways, since CVD oxides (SiOx and SiOC) and spin-on polymers already well developed will be used, while established lithography and etching technologies will complete the integration. EDN's Ron Wilson covered many of the latest air-gap integration details from IITC in his fine blog, but the most important consideration is that no new manufacturing tools are needed to make them happen. Designs may need to be tweaked, and the process integration will be challenging, but this approach is relatively low-risk and may be integrated into older fab lines.

Further proving that “there is no more noise (…there is only signal),” IMEC’s Michele Stucchi at IITC examined the effects of inherent line-edge roughness (LER) and via misalignments on the Efield and electrical breakdown between wires. An enhanced electrical field between adjacent lines is induced by LER-induced reduction in spacing. Compared to a nominal electrical field between lines with zero LER, a probabilistic analysis results in enhancement to the field, which can be a factor >2 in 30nm spaced lines. For wires with 30nm spacing, Efield may be high enough to guarantee at least one bridge in 20μm of line length. For via misalignment of 10nm in standard dual-damascene structures with 30nm spacing, the field enhancement can be a factor >3.

An amazing example of tricky process integration to eliminate variability in lithography was shown by Matthew Breitwisch of IBM, in describing work with Macronyx on phase-change memory (PCM) technology. Ge2Sb2Te5 (GST) was the first material investigated which changes from a high-resistance amorphous structure to a low-resistance crystal at ~170°C. A PCM cell is made up of a variable resistor in series with an access device (which may be a diode, BJT, or FET), and current flux near one million A/cm2 is needed for a few nanoseconds to create the change. To concentrate the current in programming, uniform small pores are achieved using a key-hole (a.k.a., “pinch-off CVD”) process:

- blanket oxide, hardmask and nitride depositions,
- lithography,
- anisotropic etching through the dielectric stack,
- an isotropic oxide etch to create an undercut below the hardmask, and
- conformal polysilicon CVD to form consistent 43nm wide keyholes.

The keyhole widths are controlled by the oxide etch and the poly CVD, and not by the lithography, such that equally sized pores form in the middle of line spaces of varying width…all without any new unit-processes.

With razor-thin process windows and systematic process-design interactions, each fab may have to optimize its own integrated process flow. If each fab runs a unique flow, then a mask-set run on one line will yield very differently on a second line, and this reality may create problems for companies trying dual-sourcing with foundries.

New materials and evolutionary upgrades to old materials will continue to support new integration schemes in fabs, while most of the tools will remain the same. However, OEM applications labs will run non-stop as fabs try new designs-of-experiments (DOE) for new integration schemes. It will be increasingly difficult to get process information out of fabs, since each line will have to be set up with unique tricks and integration schemes. Designers will have to really start innovating, as digital CMOS shrinks no longer guarantee lower cost and higher performance.

There will be many IC types that will probably never be designed at the 32nm node. A friend working on a graphics processing chip explained to me that they needed to go to 65nm to get a speed improvement for their target application, but their modeling shows that additional speed will now provide no user benefit. Going to 45nm adds huge design costs and manufacturing yield risk, and so they now plan to stick to 65nm but work on cost and power optimization in re-design. Their next 65nm chip may use 3D interconnects or integrated passives for improved performance, however, so innovation will continue… just in new directions. Such is the blessing/curse of “living in interesting times.”

Henceforth, my challenges will be elsewhere. This is my last blog post on my last day as a Technical Editor for Solid State Technology magazine; I am resigning to pursue other interests, first of which will be an immediate 8-week sabbatical. When I return, I will probably work for the semiconductor manufacturing industry, in an as-yet undetermined capacity that doubtlessly will be "interesting." I thank PennWell Publishing for years of rewarding employment, and wish the company well. Special thanks to James Montgomery, who diligently and masterfully copy edited most of these 76 postings.

—E.K.

Labels: 32nm, 3D, airgap, CMOS, copper, IITC, integration, interconnect, process, research

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080613: Process integration drives the IC industry

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Ed’s Threads 080602
Musings by Ed Korczynski on June 2, 2008

IITC shows the way to 3D
The 11th International Interconnect Technology Conference (IITC) started today in Burlingame near the San Francisco airport. Once again, the leading-edge of on-chip interconnect technology developments were presented, with details on new materials, processes, and structures. 3D interconnects and through-silicon vias (TSV) were discussed in serious detail, while work continues on air-gap dielectrics and carbon nanotubes (CNT) along with new copper barrier materials.

3D with TSV may be considered as the ultimate interconnect concept, since stacked chips provide optimal functionality/volume, and provide for relatively low-cost heterogeneous integration of diverse technologies such as sensors. TSV and the many variations thereof have been hot topics in 3D for many years, with “via-last” being done today in production for memory stacks needing typically <100 TSV per chip. In contrast, “via-first” TSV processing flows may produce thousands per chip, and there are many integration schemes possible. IITC publicity chairman (and IBM researcher) Michael Shapiro commented that, “3D is such a ‘silicon-centric’ process technology that the IITC is really the place to have the discussion, because all the experts of silicon etching and planarization are here and have always been here.”

Fraunhofer IZM (Institute for Reliability and Microintegration) in Munich has been leading the world in 3D-IC work for over ten years, and researchers from there have been developing detailed system-level heterogeneous integration schemes for wireless applications (for the European 3D integrated sensor program “e-CUBES”). Their target is die-to-wafer (D2W) stacking of a tire pressure monitoring system (TPMS). The wafer has the microcontroller chips, onto which are stacked chips for the RF transceiver, pressure sensor, and bulk acoustic resonator (BAR). For TSV, they integrate chips with both solid metal trenches (typically W filled ~20 µm deep) or hollow vias coated with doped poly-silicon (through the 300 µm thick pressure sensor).

Researchers from Georgia Tech built upon work they first showed three years ago at IITC, and together with IBM and Nanonexus showed real results of using integrated microchannel cooling to remove heat from 3D-IC stacks. Fluidic microchannels were fabricated at the wafer-level using four lithography steps, and the resulting chips showed thermal resistance of just 0.24°C/W compared to 0.6°C/W for equivalent 65nm node air-cooled chips. With reduced thermal resistance, significant advances in speed, power, and/or operating temperature can be achieved; for example, power could be reduced ~20% at the same frequency, or the frequency could increase 10% at the same power.

Basic materials integration challenges of 3D integration were shown in two presentations by IMEC. Micro-Raman spectroscopy (µRS) was used to determine the plastic yield criterion for an accurate finite element modeling (FEM) of the stress near Cu-filled TSV. Due to the inherent mismatch between CTE of Cu (16.7 ppm/°C) and Si (2.3 ppm/°C), some strain will be inherent, and it may degrade electrical carrier mobility. Defining an “exclusion zone” of transistors from the TSV such that mobility degrades <5%,>
IMEC researchers also looked at reliability in a presentation on “Resistance to electromigration of purely intermetallic micro-bump interconnections for 3D-device stacking.” Both Cu-Sn and Co-Sn were shown to withstand 1000 hours of testing at the extremely aggressive conditions of 150°C and 0.63mA/µm2).

Scott Pozder of Freescale Semiconductor showed an excellent poster on Cu-Sn microconnects formed simultaneously with an adhesive dielectric bond using thermal compression bonding of flipped dice on a wafer. After D2W bonding using Cookson F602 material at micropad pitches of 59, 64, and 69µm, the robustness of the bond was shown by grinding the bonded dice to 50µm thin using a Disco Hi-Tec tool. While no TSV are used in this die-to-wafer stack, this pragmatic approach based on standard unit-processes which can be found in the open foundry market shows one clear way forward toward 3D today.

Tohoku University researchers showed one way to cut costs in D2W bonding: use a rough lithographic step to form hydrophobic and hydrophilic areas on the wafer, add an aqueous coating and then roughly place the dice. The surface tension of the liquid induces the dice to self-align, and control of the ambient can allow for the liquid to evaporate which temporarily bonds the dice to the wafer. The average alignment accuracy on 100 dice was ~0.5µm, with most dice aligned within <1µm and all <1.5µm.

D2W stacking of 3D chips allows for the used of known good dice (KGD) and the associated minimization of yield losses anticipated with wafer-to-wafer (W2W) stacking. D2W stacking technology will first follow Freescale’s lead by flipping the top die for two levels of silicon, but TSV and three or more levels will certain follow.

Much of the limitation in the use of TSV today remains with the designers; lacking EDA tools, it is not only difficult to optimize a design for 3D, it is challenging to just try to quantify the potential benefits in advance. Until EDA tools are ready the greatest potential value of 3D stacking will not be seen, and most commercial TSV will continue to be used for memory stacks and CMOS image sensors.

This is the last year in which interconnect technologists living in the San Francisco bay area have the exclusive luxury of the International Interconnect Technology Conference being local. Next year (June 1-3, 2009), the 12th IITC will occur in Sapporo, Japan at the Royton Sapporo hotel. The 2010 meeting will be back in the San Francisco bay area, and then the 2011 meeting is expected to occur somewhere in Europe.

—E.K.

Labels: 3D, IITC, interconnect, silicon, stack, through-silicon via, TSV

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080602: IITC shows the way to 3D

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Labels: CNT, graphene, IITC, interconnect, MRS, through-silicon via

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080407: CNT and graphene dreams may be real

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Ed’s Threads 080225
Musings by Ed Korczynski on February 25, 2008

Interconnect technology mature
On-chip interconnects made primarily of copper metal insulated with SiOC low-k dielectric material are the current state-of-the-art for the commercial IC manufacturing industry. A report from the TECHCET Group quantifies the materials that are forecasted to be needed to form interconnects for 65nm to 32nm node ICs. Except for some new barrier layers, the only major change on the interconnect horizon is the use of pores or air-gaps in the dielectric material to get to ultra low-k (ULK, a.k.a. extreme low-k or ELK).

Though carbon nano-tubes (CNT) have been considered as new conductors, and self-assembled dielectrics have also been investigated, commercial IC fabs are necessarily slow to change proven technologies, and so it is almost certain that these newer approaches will not be used for commercial IC manufacturing anytime soon.

From first principles and reasonable modeling, we know that Cu is not the ultimate electrical conductor, but lacking room-temperature superconductors and ways to form dense arrays of metallic CNTs, the only near-term solution is to use more and more copper layers as a method of dealing with higher resistance copper in smaller lines. With Cu pushed to the limits, it is axiomatic that current density inside minimum pitch lines is huge such that electromigration induced reliability problems are inherent.

Cu lines in advanced dual-damascene interconnects are already complex structures, with barrier layers to prevent Cu diffusion into low-k dielectrics. An ideal Cu barrier inhibits electromigration, though any barrier is more resistive than the Cu itself, so it should be as thin as possible to minimize resistivity without allowing for Cu diffusion. For the 32nm node, Copper Manganese (CuMn) and Ruthenium barriers have been investigated, in part due to the integration advantage of being able to electro-plate Cu directly on either barrier without the need for a PVD Cu “seed” deposition. If CuMn is used, then some of the Mn diffuses to the surface of the Cu during metal anneal, and removing this surface Mn during the CMP step results in lower via resistance due to a direct Cu-to-Cu bond.

For cap layers, silicon nitride has been used at ≥90 nm, but it has a rather high dielectric constant of ~7, so SiCN with a dielectric constant of ~5 has been used at 65nm. For 32nm the most likely capping barrier may be CuSiN—formed by reacting the post-CMP Cu with SiH4 and NH3—or CoWP.

Dielectrics technology has never met the wishes of the ITRS for a different material for each node. With the k-value stuck at ~2.7 for a blanket SiOC film, the only practical solution to lower k has been to substitute “air” (a low-pressure vacuum, really) as part of the dielectric material. The air can be in random zero-dimensional “pore” (or nanopore) structures in the material, which may be formed by sublimating the homogeneously-nucleated 2nd-phase of a deposited blanket film. The air can be in random or ordered one-dimensional “air columns” in the material, as shown by Edelstein et al. at IBM. The air can also be in patterned two- and three-dimensional “air-gaps” formed by many different process flows, as shown by Hoofman et al. at Philips/NXP.

Conformal dielectric CVD processes can also be tuned to automatically form air-gaps between lines—known as “key-holes” or “bread-loaves” due to the characteristic shape of the gap when viewed in cross-section—for metal line spaces of a certain pitch. Standard dielectric CVD processes are tuned to avoid air-gaps in random line spaces so that gaps do not appear spontaneously in some portions of a random IC design. Key-hole air-gaps as desired dielectric structures were first reported by Shieh et al. of Stanford in the pages of SST in 1999, and the major limit with their use has been the need to impose design constraints on metal line pitch.

However, it now appears certain that nearly all 32nm node ICs will be made with restricted design rules just so that lithography will work. Likewise, CMP and Etch uniformity specifications at 32nm seem to mandate severe restrictions on geometry and the extensive use of “dummy fill” beyond all precedent. If a design must already deal with such limitations, then why not integrate in key-hole air-gaps by CVD? Alternatively, like IBM or Matsushita, you can use a non-critical lithography masking step and etching to define the air-gap locations independent of line pitch.

Lest we forget, aluminum metal is still used as the on-chip interconnect for some 65nm node memory chips. Proven process technology is replaced only when IC performance mandates a change, and so evolutions happens far more often than revolutions.

—E.K.

Labels: copper, dummy fill, interconnect, low-k, ULK

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080225: Interconnect technology mature

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Ed’s Threads 080222
Musings by Ed Korczynski on February 22, 2008

TSV forecast for millions of wafers
Through-silicon vias (TSV) can be used to connect 3D multi-chip module stacks with improved performance and reduced timing delays. A new report by analysts at TechSearch International, Through Silicon Via Technology: The Ultimate Market for 3D Interconnect, provides a forecast for millions of silicon wafers to be made with TSV in the year 2014. For the next few years, however, it is likely that image-sensors and memory chip stacks will be the major high-volume applications, building on the estimated less than 50,000 wafers to be fabbed with TSV this year according to TechSearch President Jan Vardaman.

The industry is now moving past the feasibility (R&D) phase for TSV technology and into the commercialization phase, where economic realities will determine which technologies are adopted. Low-cost fine via hole formation and highly reliable via filling technologies have been demonstrated; process equipment and materials are available. Global research organizations are looking at applications for TSVs including image sensors, flash, DRAM, microprocessors, FPGAs, and power amplifiers.

There is no question that 3D TSV will be adopted, but the timing for mass production depends on how the cost of the new technology compares with that of existing technologies. In particular, as confirmed by Vardaman, if there are only 2 silicon layers to be assembled it is generally more cost-effective today to use flip-chip with wire-bonders. Another 1 or 2 chip layers can be easily added to the bottom side of an interposer, still without the need for TSV.

In so doing, the wire-bonds are not in any way limits on system performance, since flip-chip bumps and re-distribution layers (RDL) are still used to route signals from chip to chip within the package. Intel has announced that its newest 45nm microprocessor chip is the first to use a thick copper RDL layer along with a polymer interconnect dielectric (presumably spun-on). A thinned memory cache chip with metal bumps (presumably C4NP or equivalent) can then be flipped onto the microprocessor and lead-free connections re-flowed to the RDL for low-latency electrical interconnects. Wire bonds then connect the stack to the package pins through an interposer.

An interposer today is commonly built-up using thin-film laminates, but there is renewed interest in the use of silicon as interposers…which would require TSV. Many companies, including MEMS foundries and equipment suppliers, today offer foundry services to create silicon interposers containing TSVs. Silicon is a wonderful material to use as an interposer between silicon chips: same coefficient of thermal expansion eliminates shear stresses on bumps due to heating, excellent relative thermal conductivity to help heat leave the chips, and excellent mechanical strength. The only problem has been the cost compared to build-up laminates. If costs can be reduced, then demand should be very elastic for silicon interposers with TSV, and we could see interposers instead of product wafers as the main near-term market for silicon TSV outside of memory stacks.

Image sensors for camera modules are already in volume production, with major investments by Tessera and Micron in wafer-level-packaging TSV manufacturing technology. The next volume application seems to be memory stacks, but it is only high-cost niche IC applications today that can justify the added cost of TSVs over wire-bonds. Design, thermal, and test issues remain a barrier to TSV adoption in some applications, though progress is being made.

Flip-chip was first introduced by IBM in the late 1960s, and it took approximately 40 years for the technology to become dominant such that more silicon wafers end up flipped instead of wirebonded today. TSV technology is already in use, but it will probably be decades before the majority of chips use it as a solution to the cost/performance trade-off challenge. The official semiconductor silicon wafer demand forecast is for ~10 billion sq.in. of silicon by the year 2010, which corresponds to ~200 million silicon wafers (in 200mm wafer equivalents) to be fabbed. It is unlikely that more than a few million of them will need internal TSV, but if costs can be reduced it is possible that many more could use silicon interposers with TSV.

—E.K.

Labels: blind TSV, interconnect, interposer, silicon, through-silicon via

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080222: TSV forecast for millions of wafers

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Ed’s Threads 070928
Musings by Ed Korczynski on September 28, 2007

Who needs through-silicon vias?
Besides MEMS and opto-electronics, who really needs through-silicon vias (TSV) for commercial ICs? This was the burning question around which presenters danced for an afternoon at the International Wafer-Level Packaging Conference (IWLPC) held this September in San Jose, California. Starting with IC and wafer-level packaging technologies already in use, experts seem confident that technology integration can create a manufacturable TSV fab flow. However, while 3D-WLP is already commercially viable (pun intended), TSV do not seem to be needed for the near future; wire-bonding already can handle up to 16 chips, and 2 level connections can be easily flip-chipped for high-performance (like for a microprocessor cache).

Ken Gilleo of ET-Trends LLC discussed the “coming paradigm shift in packaging” caused by TSV and wafer-level packaging, asserting that significant technology development has occurred with unit processes in recent years such that the main technology hurdles remain with integration.

Leslie Lea, CTO and deputy CEO for STS, explained how deep reactive-ion etch (DRIE) for TSV on 300mm wafers will still use a derivative of the sequential “Bosch Etch” process, using the C4F8 plasma for polymer sidewall deposition, then SF6 plasma for etching. This process can produce vias to 80:1 aspect ratios, but sidewall scallops inevitably exist. Cu-TSV plating time shown was 4 hr for 50µm via, while 10µm via filled in 1 hr using NEXX systems and Enthone chemistry to create via fills without voids—with vias of 10-50µm depths all nicely filled on the same chip.

TSVs have been demonstrated in four different approaches and integration schemes: blind, poly, tungsten, and copper. Jim Walker, research vice president for Gartner Dataquest, suggests that we all should use the standard PCB term “blind vias” for essentially the same structures in silicon. Unlike the other three, ‘blind’ vias don’t include the conductor, but etch/drill out openings through an upper silicon chip, typically to allow a wire bonder to make connections to bond-pads on a lower silicon chip.

These are not new. Back in 1989 I developed a pilot process for a 3-level WLP using blind TSVs for an accelerometer chip for SenSym (Analog Devices’ designers were much smarter and their planar chip design was far more manufacturable and lower cost, so sadly for me at the time the chip was killed at pilot). Blind TSVs can be combined with flip-chip stacks and C4/C4NP bumping to get to three or more silicon layers with relatively low cost and minimal disruption of current packaging flows.

Blind TSVs are another way that wire bonders may continue to function as the ‘work-horses’ of packaging lines, working with KOH or EDPW wet-etches to form sloped openings along the crystalline planes in silicon. In an exclusive meeting with WaferNEWS, Giles Humpston, director of R&D for Tessera, explained that the company’s ~$100M investment in optical-WLP technology built on the acquired ShellCase technology for blind TSV applied to the unique requirements of image-sensors and quartz substrates.

Filled vias with poly, tungsten, or copper are the TSV ideal that many of us have conceived of for 3D ICs. If design and test software could handle it, and if integration can be as low as $200/wafer (EMC-3D goal), then these TSV might be first used to stack like devices like memory parts. Phil Marcoux, longtime packaging technology expert currently with Chip Scale/TPL Group, thinks that full integration won’t be ready for five years. Gilleo countered that in 2008, “some memory will use TSV.”

Citing first principles of electrical interconnection—going back to the use of copper in the first US printed circuit board patent in 1902—Gilleo is convinced that ultimately copper is the way to go for filled TSV. Used both for PCBs and on-chip interconnects, there is a tremendous amount of proven technology that can be borrowed to speed up TSV integration. “It’s well controlled in electroplating, and it has the right balance of chemical and mechanical properties,” informed Gilleo. It becomes the nature selection for the conductor. “It has almost everything you want for building conductor pathways.”

All of this was known to the early pioneers of the planar IC at Fairchild Semiconductor. And yet they chose aluminum over copper, because copper is more reactive and can more easily diffuse into silicon and damage transistors. Copper will always have a much higher expansion with temperature compared to silicon, and so high-temperature processes will inherently stress barrier layers. Polysilicon can be annealed and then have the same expansion with temperature as the silicon wafer. Of course, polysilicon conductivity is always lower than copper, so there are trade-offs in the TSV conductor choices.

While debating whether to consider integrating poly or copper or even tungsten plugs, a gold wire bonder has already made the connection. Packaging moves fast.

--E.K.

Labels: 3D, blind TSV, copper, IC, interconnect, stack, through-silicon via

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070928: Who needs through-silicon vias?

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Ed’s Threads 070713
Musings by Ed Korczynski on July 13, 2007

High-k, low-k, special-k, super-k
SEMATECH has announced that the R&D; organization has developed a “super High-k” dielectric for ICs. How “super” can it be at 30-40 k (double the 15-20 k of hafnium oxide)? How easy might it be to integrate? We can’t guess since the material and its properties beyond the dielectric constant remain secret. All we know is that some people want us to call it “super-k” or “SHK”, and I’m against this as title inflation.

As the semiconductor manufacturing industry pushes the limits of CMOS architectures to ever smaller physical dimensions—45nm node production now ramping—materials properties must improve to ensure proper IC function. New materials are used throughout the chip, yet some of the basic terms used to describe these new materials were never standardized. In particular, the dielectric constant (k)—the measure of a material’s polarizability by a passing electromagnetic wave—was formerly kept in a tight range by using only silicon oxide (k~4) and silicon nitride (k~7) films. With 4-7 established as the “medium” range of k by default, anything <4>7 counts as “High-k” (HK). Note that industry convention capitalizes “High” while not capitalizing “low” in these terminologies. Also note that "k" is properly itallicized but does not always appears as such.

Now 45nm node chips will employ materials with k values ranging from 2.5 to 20, and even lower and higher k materials are under development. Relatively higher k is desired in transistor gates to ensure minimal current leakage when biasing the gate to open the channel, while relatively lower k is desired in intermetal dielectrics (IMD) to ensure minimal coupling and delay to propagating signal pulses.

As the industry has developed low-k dielectrics for IMD, and High-k dielectrics for gates (as well as for memory storage), terminology has been confusing.

Looking first at low-k, the industry first used fluorinated silicon-oxide glass (FSG) with k~3.5, then silicon oxycarbide (SiOC) and silicon-carbon oxyhydride (SiCOH, often pronounced “psycho”) films with k~3.0 for IMD. Since air or vacuum has k of 1, adding pores or gaps to SiCOH as a fraction of the volume proportionally decreases k for the final film. Porous low-k (PKL) films may also be termed ultra low-k (ULK) or extreme low-k (ELK), regardless of where they fall in the 2.0-2.7 range.

Polyimide, benzo-cyclo-butene (BCB), and parylene are all 2.5-3.0 k range films used in passivation and packaging, though they are not commonly termed ULK or ELK. So, for a given chip, it’s possible that a porous SiCOH film of k=2.6 would be termed ULK, while the k=2.6 BCB film used on the same chip is merely “low-k”.

Terminology moving in the other direction was formerly simpler. Starting with k ~7 for silicon nitride as the top end of the “medium” k range, the industry currently uses aluminum oxide and hafnium oxide as HK films in the 8-10 and 15-20 ranges, respectively. Less publicized in recent years but used in volume production nonetheless, ferroelectric RAM (FRAM) fabs use lead-zirconium-titanate (PZT) and barium-strontium-titanate (BST) materials with k values in the 100-300 range. For years, any dielectric with k>7 was simply termed “High.”

Now that SEMATECH wants to call 30-40 the “super” dielectric constant range, what are we to call k>50? Shall we follow the hard-disk drive (HDD) industry terminology for magneto-resistive heads and call PZT films “giant-high-k” and BST films “colossal-high-k” starting now? What about the poor FRAM marketeers who suffered without having these terms to describe their products for so many years—who could they sue for lost brand-value? Why not retroactively inflate terminology for other materials and call graded-SiON and ONO-stacks “special-k?”

In all seriousness, we should employ moderation in terminology, and just call this new material another high-k (HK). In the name of simplification, that to me would indeed be "super."

—E.K.

Labels: dielectric, high-k, IC, interconnect, low-k, metal gate, terms

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070713: High-k, low-k, special-k, super-k

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Ed’s Threads 070608
Musings by Ed Korczynski on June 08, 2007

IITC 2007: Airgaps & chip-stacks
Airgaps and 3D-stacks were the big news from the 10th International Interconnect Technology Conference (IITC) recently held near the San Francisco airport. Two major new materials was presented—IBM showed rhodium (Rh) electro-chemical deposition (ECD) for ≤32nm contact plugs, and Fujitsu showed nano-clustered silicon (NCS) with low k=2.25 for a dielectric—but most new work involves the same materials combined in clever new ways. Airgap technology was covered in four oral presentations, three posters, and countless informal hallway discussions.

Dan Edelstein, IBM Fellow and manager of BEOL technology strategy at Yorktown Heights, NY, gave an invited talk on the many integration challenges for 32nm node interconnects, including resist poisoning from low-k outgassing, low-k damage removal, and the need for improved thin-film interfaces. “We need to keep adding innovation just to stay on the trend-line,” he commented. For example, the industry has historically seen chronically low SiCOH low-k adhesion on SiCHN barrier layers—regardless of equipment, CVD precursor, or plasma preclean—due to a carbon-rich initial deposition. Adding a diverter-valve to the tool allows for stabilized precursor flow before RF power is turned on, which eliminates the carbon-rich deposition and thus solves the adhesion issue. With subtle integration challenges such as these, IBM has chosen to add airgaps as a side-loop with no new materials, tools, or baseline processes. Airgaps drop k by ~35% for any given dielectric material, Edelstein noted, adding that IBM has “shown this on gapped SiOF and low-k SiCOH, and will do it next on ULK porous SiCOH.”

The IBM airgap process both removes and re-deposits some dielectric material, while most airgap approaches for logic chips rely on removal processes alone. The Crolles2Alliance (CEA-Leti, Freescale, NXP, and ST) uses SiO2 at line-levels and a polymer for the via-levels within the dielectric stack, then HF vapor or wet-etch-chemistries to remove the SiO2. NXP and Dow Chemical showed removal of a thermally degradable polymer (TDP) through a CVD SiOC cap layer to make ~30% airgaps at M2 as part of a keff ~2.5 to hit 32nm node specs.

The Crolles2Alliance also showed some of the integration tricks needed to use porous ULK dielectrics at the 32nm node. Different plasmas may seal pore surfaces to provide barrier properties for long-term reliability: CH4 adds C, NH3 substitutes N for C leading toward SiON compositions, and He/H2 plasmas retain near original stoichiometry. Though Cu bulk resistivity is only ~2.2 µOhm-cm, for 60nm line widths it is ~2.9 and increases with reducing widths. CMOS32 uses 50nm Cu line widths for M1, requiring a self-aligned barrier (SAB) <4nm for EM performance, an ALD barrier and thin-Cu seed for filling, and either a CuSiN or CoWP cap layer.

NEC research labs showed that direct ECD of Cu without a Cu-seed layer provides larger grain size and higher Cu(111) orientation. Damascene structures were first sealed with TiN, then either Ta/Cu or Ru layers were deposited. The TiN barrier layer is definitely needed beneath Ru to block Cu diffusion into the dielectric. Ru PVD using DC magnetron sputtering with Ar gas at room temperature produces high orientation of Ru(002). Since Ru(002) is hexagonal-close-packed, it matches well with the preferred Cu(111) face-centered-cubic orientation such that 40%-50% can be grown directly on Ru in dual-damascene structures. Some day, metal line specifications may include not just dimensions and resistivity, but grain orientation and size-distribution too.

Ibaraki U. and Hitachi presented research showing that higher chemical purity leads to lower resistivity in Cu lines. Increasing both the Cu anode purity from 4N to 9N along with the CuSO4·5H2O purity from 3N to 6N reduced line resistance by 21% in 50nm wide lines, with all other process parameters held constant. The high-purity process increased the average grain size from 70 to 74nm, and significantly reduced the oxygen content in the final annealed Cu lines to <1 wt% from the previous 3-4 wt%.

Based on first principles of thermodynamics, an alloy of Cu/Mn can be annealed to result in self-segregation of Mn to the dielectric/Cu barrier. One fundamental advantage of this process is that no barrier is formed at the bottoms of vias, which minimizes resistance. Toshiba’s R&D; group tested self-aligned Mn barriers with 244-via-chain structures and found one-third the resistance compared to Cu vias using the standard Ta barrier.

Georgia Tech and U. of New Mexico researchers showed that a 60% increase in the total number of wire levels is sufficient to account for ~5x increase in the resistivity of wires. Careful routing and a logical hierarchy seem to go a long way, but eventually the industry must get serious about 3D ICs using chip-stacks.

Patrick Leduc of CEA-Leti provided an overview of the main challenges to realizing high density 3D ICs: bonding with ±1µm alignment at T<400°C, Si thinning to <15µm, and through-silicon via (TSV) diameters <3µm. Thermal management issues may not be too difficult—assuming each transistor contributes 0.7W to a 50 W/cm2 average—since bulk silicon acts as an efficient heat spreader and the metal lines conduct well.

Freescale’s Scott Pozder explained that EDA software tools may be the current biggest limitation to 3D integration, since standard tools cannot even account for metal levels on multiple chips. If you explicitly design for 3D, then models show that multiplicative yield-losses can be avoided or eliminated.

There were ~480 conference attendees this year (plus several hundred additional folks running evening supplier-seminars and exhibit booths). Among the attendees with whom I enjoyed discussions were (in alphabetical order) Al Bergendahl, Chris Case, Paul Feeney, Terry Francis, Mike Fury, Xiao Hu Liu, Steven Luce, Satya Nitta, Mike Shapiro, and a special appearance by casually retired Mike Thomas.

—E.K.

Labels: airgap, copper, dual-damascene, IITC, interconnect, low-k, self-aligned barrier, ULK

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070608: IITC2007 airgaps & chip-stacks

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Ed’s Threads 070525
Musings by Ed Korczynski on May 25, 2007

Intel-IBM fab hype-war and truths
It has been said that the first casualty of war is the truth…even more so in a hype-war. An interview appearing on a popular electronics industry Web site is the most recent battlefield in this ongoing hype-war between the world’s semiconductor manufacturing heavyweights. As tradeoffs in fab technology become more fundamental at 45nm nodes and beyond, different companies choose to deploy similar technologies in different ways. The truth is inherently complex and thus a bit complex to describe, and can die under the assault of hype.

Among fundamental choices today we find the following: double-patterned dry or single-patterned wet lithography for critical layer patterning, and use of porous or airgap low-k dielectric for on-chip multi-level interconnects. Intel has chosen double-patterned dry lithography and non-airgap low-k dielectrics. IBM has chosen single-patterned wet-lithography and airgap dielectrics.

As shown by Hoofman, et.al, in the pages of SST last year, there are many different airgap process flows, which can produce many different airgap structures. Airgaps may be complete or partial between lines, and this is one of the more fundamental parameters to consider in integrating the structures into real chips. Thus, airgap1 is not airgap2 (General Semantics suggests the use of “indexing” to remind us of the essential distinctions between members of any conceptual set).

Using “complete airgap” flows and removing all dielectric between lines to achieve the absolute minimum capacitance does indeed create the two general problems articulated by Mark Bohr in the recorded interview: an expensive critical-lithography mask to ensure proper via landings, and copper electromigration sensitivity. However, the IBM flow uses airgaps only in the middle of line spaces while leaving dielectric material on the sidewalls of copper lines.

The IBM airgap process exposes parts of some metal sidewalls during the tricky three-stage gap etch, but the subsequent dielectric CVD process re-coats the exposed sidewall areas prior to “pinching off” the tops of gaps. With adequate sidewall dielectric in place, via landing and electromigration issues can be minimized if not avoided. Intel’s Bohr certainly understands airgap integration issues far better than I do, but because he’s not in a position to comment on how his competitor’s process might work, he accurately and properly expressed Intel’s results in the interview, and the generic disadvantages of approaches not currently taken by Intel.

However, a statement summarizing the interview reads thusly: “Mark Bohr, Intel senior fellow, says his company looked at air-gap technology like IBM recently introduced, and dismissed it as costly and inefficient.” That's a misinterpretation. The truth is that Intel never panned IBM’s airgap technology—Bohr answered a specific question about IBM’s technology with a generic answer about non-IBM technology. Of course, Bohr can very reasonably say that he has no knowledge if IBM’s technology beyond what is muddied in the official press release. Since IBM’s marketing spun the technology truth to the point of grandiose hype, it provides easy opportunity for Intel to comment on the hype instead of the truth. (Incidentally, further information on the general concept of self-assembled nanotechnology for lithographic masking applications can be found in the most recent issue of Microlithography World.)

The IBM hype was that no new lithography is needed. Intel counters that a generic process flow for airgaps requires critical-lithography steps. The truth is that the IBM flow does use an additional lithography step for each airgap level, but it’s non-critical and the mask generation has been automated as a button in the EDA deck. Critical-lithography steps for 45nm node processing can be 10X more expensive than non-critical patterning steps. If the IBM airgap process required critical lithography for each level then it might add 20%-25% to the cost of each chip, but with non-critical lithography it might add only 5%-8%.

For most people in the world who lack experience in fab processes, subtle complexities get lost in translation and details are distorted or lost. The truth about nanometer-era fab processes is that they are all tough to develop with inherent integration trade-offs. With Intel and IBM now going down divergent paths, it’s truly difficult to assess a fab technology “leader” in anything but hype.

— E.K.

Labels: airgap, fab, IBM, IC, Intel, interconnect, low-k, self-assembly, ULK

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070525: Intel-IBM fab hype-war and truths

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Ed’s Threads 070504
Musings by Ed Korczynski on May 04, 2007 (updated June 12, 2007 to correct details of the IBM airgap etch process, which had erroneously referred to the third-step being RIE, when it is wet as confirmed by both D. Edelstein and S. Nitta)

IBM adds airgaps for faster chips
Airgaps have long been considered as structures to increase the speed of on-chip IC interconnects, though no one had developed manufacturing-worthy process flows. Only in the last year have companies such as Philips (now NXP) shown overviews of likely airgap manufacturing processes, though without production commitments. Now IBM has invented a new variation on airgaps that uses a self-assembling polymer mask layer as part of the process flow, and claims this can be a simple drop-in addition that adds only ~1% to chip cost for each dielectric layer gapped. Thus for an advanced multilevel interconnect, a ~5% cost adder should provide 35% faster chips or 15% less power consumption.

Circuit speeds are limited by the dielectric constant (k) of the insulating material surrounding metal lines, so the industry's Roadmap has focused on ever lower k dielectric materials. Unfortunately, materials engineering for a new dielectric material is difficult and expensive, and despite tremendous efforts and many false-starts over the years, the entire world has now settled on SiCOH by CVD as the lone dielectric material (k~3) that provides acceptable cost, yield, and reliability. So-called ultralow-k (ULK, aka “extreme low-k”) films are merely k~3 SiCOH with the addition of ~20%-40% by volume of nanopores to reach k~2.4. More nanopores cannot be added without degrading yield and reliability, so the only practical way to get to k~2 is to incorporate a single large pore with clever processing as an “airgap.”

A multiyear development effort to create a manufacturable airgap process was led by IBM fellow Dan Edelstein, program manager for low-k CVD BEOL, who provided Solid State Technology and WaferNews with exclusive insight into how they achieved these remarkable results. He explained that unlike previously known airgap process flows, the IBM approach starts with a standard dual-damascene copper and SiCOH dielectric process that has been in production for years. Airgaps are formed using a multi-step etch, using a hardmask patterned with either self-assembling monolayers or standard lithography depending upon the geometry of the interconnect.

Unfortunately, IBM's press release touting the airgap achievement is so grossly hyped that it’s caused severe misunderstanding throughout most press reports on this process. The new technique "skips the masking and light-etching process,” says the official release. “Instead IBM scientists discovered the right mix of compounds, which they pour onto a silicon wafer with the wired chip patterns, then bake it.”

In reality, while self-assembly can be used to make an array of nominally 20nm holes by spin-coating and baking, these holes merely pattern the hardmask that is used to etch the gaps into the dielectric, explained Edelstein. A non-critical lithography step is used to block out circuit areas that do not need gaps, he said. The self-assembly layer is not even used to pattern the hardmask used to make airgaps at upper levels of the interconnect. “At some point in the hierarchy it becomes more viable to use lithography instead of self-assembly,” he said.

While IBM doesn't use airgaps for the first level of metal, they could be used at any of the higher levels within the hierarchical interconnect stack, Edelstein noted. “Most chips won’t need air-gaps on all levels, but perhaps on half,” he said.

No matter the level, a special three-step etch process to form gaps with narrow top openings is the key to this process (see figure). “We etch a narrow channel down so it will cap off, then deliberately damage the dielectric and etch it so it looks like a balloon,” he explained. “You have a big gap with a drop in capacitance and then a small slot that gets pinched off.”

Starting with dual-damascene copper lines/vias and SiCOH single-phase dielectric, the essential IBM airgap process flow is as follows:

1) Deposit hardmask;
2) Spin-coat an imaging layer; either special new diblock polymer or standard photoresist;
3) Create holes using either the self-assembly properties of the diblock or standard lithography;
4) Block out circuit areas to not be etched using non-critical photolithography;
5) Transfer holes from the imaging layer to the hardmask;
6) Etch three-step sequence—first an anisotropic RIE to form deep openings into SiCOH, then plasma damage of the column sidewalls, then isotropic wet etch to remove most of the remaining SiCOH underneath the hardmask;
7) Strip hardmask; and
8) PECVD of the next SiCOH dielectric level to cap the gaps with a classic “pinch-off” shape.

Since the self-assembling mask layer is not aligned to the underlying interconnect structures, and since the block-out mask is “non-critical” to save costs, the hardmask will inevitably expose the tops and sides of some metal lines to RIE. Consequently, the SiCOH etch chemistry needs to have excellent selectivity so as to not attack copper and any metallic barrier layers. Edelstein says that they’ve been able to work with standard gas precursors for this critical RIE step.

The new airgap process is an optional loop off of the standard flow, so designers can choose to use airgaps at any of the levels in the on-chip interconnect hierarchy—and IBM also has developed an automated algorithm for making the block-out mask. “As a customer you can turn on the air-gap option for any level on any chip. We can put the gaps in independent of any incoming design,” Edelstein told WaferNEWS. The ability to add air-gaps as a “drop-in” to an existing on-chip interconnect process flow minimizes risks, and explains the company’s confidence that this flow will be used in manufacturing by 2009.

While the diblock polymer is only one part of this airgap process, it is a significant addition. Chemists at IBM Almaden Research reportedly developed this material for broad applications in fabs—it’s like a standard photoresist in terms of handling and dispensing, it has a wide process window, and IBM has detected no shelf-life problems for up to one year.

Using self-assembly in coordination with lithography opens up new possibilities in general for integrated process flows, so look for news of additional applications in coming years. “We hope that we can use directed self-assembly to get to other device features,” said Edelstein. “This is just the tip of the iceberg.”

— E.K.

Labels: airgap, fab, IBM, IC, interconnect, low-k, self-assebly, ULK

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070504: IBM add airgaps for faster chips

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